STATISTIC(NumLoads , "Number of loads added");
STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
-namespace {
- static RegisterRegAlloc
- bigBlockRegAlloc("bigblock", " Big-block register allocator",
- createBigBlockRegisterAllocator);
+static RegisterRegAlloc
+ bigBlockRegAlloc("bigblock", "Big-block register allocator",
+ createBigBlockRegisterAllocator);
+namespace {
/// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
/// keys.
struct VRegKeyInfo {
class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
public:
static char ID;
- RABigBlock() : MachineFunctionPass((intptr_t)&ID) {}
+ RABigBlock() : MachineFunctionPass(&ID) {}
private:
/// TM - For getting at TargetMachine info
///
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
" the intended one.");
- DOUT << " Spilling register " << RegInfo->getPrintableName(PhysReg)
+ DOUT << " Spilling register " << RegInfo->getName(PhysReg)
<< " containing %reg" << VirtReg;
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
assignVirtToPhysReg(VirtReg, PhysReg);
} else { // no free registers available.
// try to fold the spill into the instruction
- SmallVector<unsigned, 2> Ops;
+ SmallVector<unsigned, 1> Ops;
Ops.push_back(OpNum);
if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) {
++NumFolded;
markVirtRegModified(VirtReg, false);
DOUT << " Reloading %reg" << VirtReg << " into "
- << RegInfo->getPrintableName(PhysReg) << "\n";
+ << RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// look for vreg reads..
- if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
+ if (MO.isReg() && !MO.isDef() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
// ..and add them to the read table.
VRegTimes* &Times = VRegReadTable[MO.getReg()];
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
+ if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
MO.isDef() && !MO.isDead())
return true;
}
static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
+ if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
!MO.isDef() && MO.isKill())
return true;
}
DOUT << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
- DOUT << "[" << RegInfo->getPrintableName(i)
+ DOUT << "[" << RegInfo->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
DOUT << "\n");
SmallVector<unsigned, 8> Kills;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.isKill()) {
+ if (MO.isReg() && MO.isKill()) {
if (!MO.isImplicit())
Kills.push_back(MO.getReg());
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
- if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
+ if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
}
if (PhysReg) {
- DOUT << " Last use of " << RegInfo->getPrintableName(PhysReg)
+ DOUT << " Last use of " << RegInfo->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Last use of "
- << RegInfo->getPrintableName(*AliasSet)
+ << RegInfo->getName(*AliasSet)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(*AliasSet);
}
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
+ if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
SmallVector<unsigned, 8> DeadDefs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.isDead())
+ if (MO.isReg() && MO.isDead())
DeadDefs.push_back(MO.getReg());
}
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.isDef() && MO.getReg() &&
+ if (MO.isReg() && MO.isDef() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
}
if (PhysReg) {
- DOUT << " Register " << RegInfo->getPrintableName(PhysReg)
+ DOUT << " Register " << RegInfo->getName(PhysReg)
<< " [%reg" << VirtReg
- << "] is never used, removing it frame live list\n";
+ << "] is never used, removing it from live set\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
- DOUT << " Register " << RegInfo->getPrintableName(*AliasSet)
+ DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet
- << "] is never used, removing it frame live list\n";
+ << "] is never used, removing it from live set\n";
removePhysReg(*AliasSet);
}
}
}
// Finally, if this is a noop copy instruction, zap it.
- unsigned SrcReg, DstReg;
- if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (TII.isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ SrcReg == DstReg)
MBB.erase(MI);
}