//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "processimplicitdefs"
-
#include "llvm/ADT/SetVector.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
+#define DEBUG_TYPE "processimplicitdefs"
+
namespace {
/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
/// for each use. Add isUndef marker to implicit_def defs and their uses.
!MI->isRegSequence() &&
!MI->isPHI())
return false;
- for (MIOperands MO(MI); MO.isValid(); ++MO)
- if (MO->isReg() && MO->isUse() && MO->readsReg())
+ for (const MachineOperand &MO : MI->operands())
+ if (MO.isReg() && MO.isUse() && MO.readsReg())
return false;
return true;
}
MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
bool Found = false;
for (++UserMI; UserMI != UserE; ++UserMI) {
- for (MIOperands MO(UserMI); MO.isValid(); ++MO) {
- if (!MO->isReg())
+ for (MachineOperand &MO : UserMI->operands()) {
+ if (!MO.isReg())
continue;
- unsigned UserReg = MO->getReg();
+ unsigned UserReg = MO.getReg();
if (!TargetRegisterInfo::isPhysicalRegister(UserReg) ||
!TRI->regsOverlap(Reg, UserReg))
continue;
// UserMI uses or redefines Reg. Set <undef> flags on all uses.
Found = true;
- if (MO->isUse())
- MO->setIsUndef();
+ if (MO.isUse())
+ MO.setIsUndef();
}
if (Found)
break;
bool Changed = false;
- TII = MF.getTarget().getInstrInfo();
- TRI = MF.getTarget().getRegisterInfo();
+ TII = MF.getSubtarget().getInstrInfo();
+ TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();
assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
assert(WorkList.empty() && "Inconsistent worklist state");