//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "phielim"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
-#include <set>
+#include "llvm/Support/Compiler.h"
#include <algorithm>
+#include <map>
using namespace llvm;
+STATISTIC(NumAtomic, "Number of atomic phis lowered");
+
namespace {
- Statistic<> NumAtomic("phielim", "Number of atomic phis lowered");
- Statistic<> NumSimple("phielim", "Number of simple phis lowered");
-
- struct PNE : public MachineFunctionPass {
- bool runOnMachineFunction(MachineFunction &Fn) {
- bool Changed = false;
-
- // Eliminate PHI instructions by inserting copies into predecessor blocks.
- for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
- Changed |= EliminatePHINodes(Fn, *I);
-
- return Changed;
- }
+ class VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
+ MachineRegisterInfo *MRI; // Machine register information
+
+ public:
+ static char ID; // Pass identification, replacement for typeid
+ PNE() : MachineFunctionPass(&ID) {}
+ virtual bool runOnMachineFunction(MachineFunction &Fn);
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
///
bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
void LowerAtomicPHINode(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator AfterPHIsIt,
- DenseMap<unsigned, VirtReg2IndexFunctor> &VUC);
- };
+ MachineBasicBlock::iterator AfterPHIsIt);
- RegisterPass<PNE> X("phi-node-elimination",
- "Eliminate PHI nodes for register allocation");
+ /// analyzePHINodes - Gather information about the PHI nodes in
+ /// here. In particular, we want to map the number of uses of a virtual
+ /// register which is used in a PHI node. We map that to the BB the
+ /// vreg is coming from. This is used later to determine when the vreg
+ /// is killed in the BB.
+ ///
+ void analyzePHINodes(const MachineFunction& Fn);
+
+ typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
+ typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
+
+ VRegPHIUse VRegPHIUseCount;
+
+ // Defs of PHI sources which are implicit_def.
+ SmallPtrSet<MachineInstr*, 4> ImpDefs;
+ };
}
+char PNE::ID = 0;
+static RegisterPass<PNE>
+X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
+
+const PassInfo *const llvm::PHIEliminationID = &X;
+
+bool PNE::runOnMachineFunction(MachineFunction &Fn) {
+ MRI = &Fn.getRegInfo();
+
+ analyzePHINodes(Fn);
+
+ bool Changed = false;
+
+ // Eliminate PHI instructions by inserting copies into predecessor blocks.
+ for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ Changed |= EliminatePHINodes(Fn, *I);
+
+ // Remove dead IMPLICIT_DEF instructions.
+ for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
+ E = ImpDefs.end(); I != E; ++I) {
+ MachineInstr *DefMI = *I;
+ unsigned DefReg = DefMI->getOperand(0).getReg();
+ if (MRI->use_empty(DefReg))
+ DefMI->eraseFromParent();
+ }
+
+ ImpDefs.clear();
+ VRegPHIUseCount.clear();
+ return Changed;
+}
-const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
/// predecessor basic blocks.
if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
return false; // Quick exit for basic blocks without PHIs.
- // VRegPHIUseCount - Keep track of the number of times each virtual register
- // is used by PHI nodes in successors of this block.
- DenseMap<unsigned, VirtReg2IndexFunctor> VRegPHIUseCount;
- VRegPHIUseCount.grow(MF.getSSARegMap()->getLastVirtReg());
-
- for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin(),
- E = MBB.pred_end(); PI != E; ++PI)
- for (MachineBasicBlock::succ_iterator SI = (*PI)->succ_begin(),
- E = (*PI)->succ_end(); SI != E; ++SI)
- for (MachineBasicBlock::iterator BBI = (*SI)->begin(), E = (*SI)->end();
- BBI != E && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
- for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- VRegPHIUseCount[BBI->getOperand(i).getReg()]++;
-
// Get an iterator to the first instruction after the last PHI node (this may
// also be the end of the basic block).
MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
++AfterPHIsIt; // Skip over all of the PHI nodes...
- while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
- LowerAtomicPHINode(MBB, AfterPHIsIt, VRegPHIUseCount);
- }
+ while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
+ LowerAtomicPHINode(MBB, AfterPHIsIt);
+
return true;
}
-/// InstructionUsesRegister - Return true if the specified machine instr has a
-/// use of the specified register.
-static bool InstructionUsesRegister(MachineInstr *MI, unsigned SrcReg) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(0).isRegister() &&
- MI->getOperand(0).getReg() == SrcReg &&
- MI->getOperand(0).isUse())
- return true;
- return false;
+/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
+/// are implicit_def's.
+static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
+ const MachineRegisterInfo *MRI) {
+ for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
+ unsigned SrcReg = MPhi->getOperand(i).getReg();
+ const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+ if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
+ return false;
+ }
+ return true;
}
/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
/// under the assuption that it needs to be lowered in a way that supports
/// atomic execution of PHIs. This lowering method is always correct all of the
/// time.
+///
void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator AfterPHIsIt,
- DenseMap<unsigned, VirtReg2IndexFunctor> &VRegPHIUseCount) {
+ MachineBasicBlock::iterator AfterPHIsIt) {
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
MachineInstr *MPhi = MBB.remove(MBB.begin());
+ unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
unsigned DestReg = MPhi->getOperand(0).getReg();
+ bool isDead = MPhi->getOperand(0).isDead();
- // Create a new register for the incoming PHI arguments/
+ // Create a new register for the incoming PHI arguments.
MachineFunction &MF = *MBB.getParent();
- const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
- unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
+ const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
+ unsigned IncomingReg = 0;
- // Insert a register to register copy in the top of the current block (but
+ // Insert a register to register copy at the top of the current block (but
// after any remaining phi nodes) which copies the new incoming register
// into the phi node destination.
- //
- const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
+ const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
+ if (isSourceDefinedByImplicitDef(MPhi, MRI))
+ // If all sources of a PHI node are implicit_def, just emit an
+ // implicit_def instead of a copy.
+ BuildMI(MBB, AfterPHIsIt,
+ TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
+ else {
+ IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
+ TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
+ }
- // Update live variable information if there is any...
+ // Update live variable information if there is any.
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt);
- // Add information to LiveVariables to know that the incoming value is
- // killed. Note that because the value is defined in several places (once
- // each for each incoming block), the "def" block and instruction fields
- // for the VarInfo is not filled in.
- //
- LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
+ if (IncomingReg) {
+ // Increment use count of the newly created virtual register.
+ LV->getVarInfo(IncomingReg).NumUses++;
- // Since we are going to be deleting the PHI node, if it is the last use
- // of any registers, or if the value itself is dead, we need to move this
+ // Add information to LiveVariables to know that the incoming value is
+ // killed. Note that because the value is defined in several places (once
+ // each for each incoming block), the "def" block and instruction fields
+ // for the VarInfo is not filled in.
+ LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
+
+ LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
+ }
+
+ // Since we are going to be deleting the PHI node, if it is the last use of
+ // any registers, or if the value itself is dead, we need to move this
// information over to the new copy we just inserted.
- //
LV->removeVirtualRegistersKilled(MPhi);
// If the result is dead, update LV.
- if (LV->RegisterDefIsDead(MPhi, DestReg)) {
+ if (isDead) {
LV->addVirtualRegisterDead(DestReg, PHICopy);
- LV->removeVirtualRegistersDead(MPhi);
+ LV->removeVirtualRegisterDead(DestReg, MPhi);
}
-
- // Realize that the destination register is defined by the PHI copy now, not
- // the PHI itself.
- LV->getVarInfo(DestReg).DefInst = PHICopy;
}
- // Adjust the VRegPHIUseCount map to account for the removal of this PHI
- // node.
- unsigned NumPreds = (MPhi->getNumOperands()-1)/2;
+ // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
- VRegPHIUseCount[MPhi->getOperand(i).getReg()] -= NumPreds;
-
- // Now loop over all of the incoming arguments, changing them to copy into
- // the IncomingReg register in the corresponding predecessor basic block.
- //
- std::set<MachineBasicBlock*> MBBsInsertedInto;
- for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
- unsigned SrcReg = MPhi->getOperand(i-1).getReg();
- assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
+ --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
+ MPhi->getOperand(i).getReg())];
+
+ // Now loop over all of the incoming arguments, changing them to copy into the
+ // IncomingReg register in the corresponding predecessor basic block.
+ SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
+ for (int i = NumSrcs - 1; i >= 0; --i) {
+ unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
+ assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"Machine PHI Operands must all be virtual registers!");
- // Get the MachineBasicBlock equivalent of the BasicBlock that is the
- // source path the PHI.
- MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
+ // If source is defined by an implicit def, there is no need to insert a
+ // copy.
+ MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+ if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ ImpDefs.insert(DefMI);
+ continue;
+ }
+
+ // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
+ // path the PHI.
+ MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
// Check to make sure we haven't already emitted the copy for this block.
- // This can happen because PHI nodes may have multiple entries for the
- // same basic block.
- if (!MBBsInsertedInto.insert(&opBlock).second)
+ // This can happen because PHI nodes may have multiple entries for the same
+ // basic block.
+ if (!MBBsInsertedInto.insert(&opBlock))
continue; // If the copy has already been emitted, we're done.
- // Get an iterator pointing to the first terminator in the block (or end()).
- // This is the point where we can insert a copy if we'd like to.
- MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
-
+ // Find a safe location to insert the copy, this may be the first terminator
+ // in the block (or end()).
+ MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
+
// Insert the copy.
- RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
+ TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
- // We want to be able to insert a kill of the register if this PHI
- // (aka, the copy we just inserted) is the last use of the source
- // value. Live variable analysis conservatively handles this by
- // saying that the value is live until the end of the block the PHI
- // entry lives in. If the value really is dead at the PHI copy, there
- // will be no successor blocks which have the value live-in.
- //
- // Check to see if the copy is the last use, and if so, update the
- // live variables information so that it knows the copy source
- // instruction kills the incoming value.
+ // We want to be able to insert a kill of the register if this PHI (aka, the
+ // copy we just inserted) is the last use of the source value. Live
+ // variable analysis conservatively handles this by saying that the value is
+ // live until the end of the block the PHI entry lives in. If the value
+ // really is dead at the PHI copy, there will be no successor blocks which
+ // have the value live-in.
//
+ // Check to see if the copy is the last use, and if so, update the live
+ // variables information so that it knows the copy source instruction kills
+ // the incoming value.
LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
+ InRegVI.UsedBlocks[opBlock.getNumber()] = true;
- // Loop over all of the successors of the basic block, checking to see
- // if the value is either live in the block, or if it is killed in the
- // block. Also check to see if this register is in use by another PHI
- // node which has not yet been eliminated. If so, it will be killed
- // at an appropriate point later.
- //
+ // Loop over all of the successors of the basic block, checking to see if
+ // the value is either live in the block, or if it is killed in the block.
+ // Also check to see if this register is in use by another PHI node which
+ // has not yet been eliminated. If so, it will be killed at an appropriate
+ // point later.
// Is it used by any PHI instructions in this block?
- bool ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
+ bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
std::vector<MachineBasicBlock*> OpSuccBlocks;
}
}
- // Okay, if we now know that the value is not live out of the block,
- // we can add a kill marker in this block saying that it kills the incoming
- // value!
+ // Okay, if we now know that the value is not live out of the block, we can
+ // add a kill marker in this block saying that it kills the incoming value!
if (!ValueIsLive) {
// In our final twist, we have to decide which instruction kills the
- // register. In most cases this is the copy, however, the first
+ // register. In most cases this is the copy, however, the first
// terminator instruction at the end of the block may also use the value.
// In this case, we should mark *it* as being the killing block, not the
// copy.
- bool FirstTerminatorUsesValue = false;
- if (I != opBlock.end()) {
- FirstTerminatorUsesValue = InstructionUsesRegister(I, SrcReg);
+ MachineBasicBlock::iterator KillInst = prior(InsertPos);
+ MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
+ if (Term != opBlock.end()) {
+ if (Term->readsRegister(SrcReg))
+ KillInst = Term;
// Check that no other terminators use values.
#ifndef NDEBUG
- for (MachineBasicBlock::iterator TI = next(I); TI != opBlock.end();
+ for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
++TI) {
- assert(!InstructionUsesRegister(TI, SrcReg) &&
+ assert(!TI->readsRegister(SrcReg) &&
"Terminator instructions cannot use virtual registers unless"
"they are the first terminator in a block!");
}
#endif
}
- MachineBasicBlock::iterator KillInst;
- if (!FirstTerminatorUsesValue)
- KillInst = prior(I);
- else
- KillInst = I;
-
// Finally, mark it killed.
LV->addVirtualRegisterKilled(SrcReg, KillInst);
}
// Really delete the PHI instruction now!
- delete MPhi;
+ MF.DeleteMachineInstr(MPhi);
++NumAtomic;
}
+
+/// analyzePHINodes - Gather information about the PHI nodes in here. In
+/// particular, we want to map the number of uses of a virtual register which is
+/// used in a PHI node. We map that to the BB the vreg is coming from. This is
+/// used later to determine when the vreg is killed in the BB.
+///
+void PNE::analyzePHINodes(const MachineFunction& Fn) {
+ for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
+ I != E; ++I)
+ for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
+ BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
+ for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
+ ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
+ BBI->getOperand(i).getReg())];
+}
projects / oota-llvm.git / blobdiff