//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "phielim"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
#include <algorithm>
using namespace llvm;
+STATISTIC(NumAtomic, "Number of atomic phis lowered");
+//STATISTIC(NumSimple, "Number of simple phis lowered");
+
namespace {
- static Statistic<> NumAtomic("phielim", "Number of atomic phis lowered");
- static Statistic<> NumSimple("phielim", "Number of simple phis lowered");
-
struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
+ static char ID; // Pass identification, replacement for typeid
+ PNE() : MachineFunctionPass((intptr_t)&ID) {}
+
bool runOnMachineFunction(MachineFunction &Fn) {
analyzePHINodes(Fn);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
VRegPHIUse VRegPHIUseCount;
};
+ char PNE::ID = 0;
RegisterPass<PNE> X("phi-node-elimination",
"Eliminate PHI nodes for register allocation");
}
unsigned DestReg = MPhi->getOperand(0).getReg();
- // Create a new register for the incoming PHI arguments/
+ // Create a new register for the incoming PHI arguments.
MachineFunction &MF = *MBB.getParent();
- const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
- unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
+ const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
+ unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
// Insert a register to register copy in the top of the current block (but
// after any remaining phi nodes) which copies the new incoming register
// into the phi node destination.
//
- const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
+ const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
+ TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
// Update live variable information if there is any...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt);
+ // Increment use count of the newly created virtual register.
+ LV->getVarInfo(IncomingReg).NumUses++;
+
// Add information to LiveVariables to know that the incoming value is
// killed. Note that because the value is defined in several places (once
// each for each incoming block), the "def" block and instruction fields
LV->addVirtualRegisterDead(DestReg, PHICopy);
LV->removeVirtualRegistersDead(MPhi);
}
-
- // Realize that the destination register is defined by the PHI copy now, not
- // the PHI itself.
- LV->getVarInfo(DestReg).DefInst = PHICopy;
+
+ LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
}
// Adjust the VRegPHIUseCount map to account for the removal of this PHI
// node.
- unsigned NumPreds = (MPhi->getNumOperands()-1)/2;
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
- VRegPHIUseCount[BBVRegPair(
- MPhi->getOperand(i + 1).getMachineBasicBlock(),
- MPhi->getOperand(i).getReg())] -= NumPreds;
+ --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
+ MPhi->getOperand(i).getReg())];
// Now loop over all of the incoming arguments, changing them to copy into
// the IncomingReg register in the corresponding predecessor basic block.
std::set<MachineBasicBlock*> MBBsInsertedInto;
for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
unsigned SrcReg = MPhi->getOperand(i-1).getReg();
- assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"Machine PHI Operands must all be virtual registers!");
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI.
- MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
+ MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMBB();
// Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the
MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
// Insert the copy.
- RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
+ TII->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
// instruction kills the incoming value.
//
LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
+ InRegVI.UsedBlocks[opBlock.getNumber()] = true;
// Loop over all of the successors of the basic block, checking to see
// if the value is either live in the block, or if it is killed in the
//
// Is it used by any PHI instructions in this block?
- bool ValueIsLive =
- VRegPHIUseCount[BBVRegPair(
- MPhi->getOperand(i).getMachineBasicBlock(),
- SrcReg)] != 0;
+ bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
std::vector<MachineBasicBlock*> OpSuccBlocks;
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- VRegPHIUseCount[BBVRegPair(
- BBI->getOperand(i + 1).getMachineBasicBlock(),
- BBI->getOperand(i).getReg())]++;
+ ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
+ BBI->getOperand(i).getReg())];
}
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