static char ID; // Pass ID, replacement for typeid
const char *const Banner;
- MachineVerifierPass(const char *b = 0)
+ MachineVerifierPass(const char *b = nullptr)
: MachineFunctionPass(ID), Banner(b) {
initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
}
- void getAnalysisUsage(AnalysisUsage &AU) const {
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
- bool runOnMachineFunction(MachineFunction &MF) {
+ bool runOnMachineFunction(MachineFunction &MF) override {
MF.verify(this, Banner);
return false;
}
}
bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
- raw_ostream *OutFile = 0;
+ raw_ostream *OutFile = nullptr;
if (OutFileName) {
std::string ErrorInfo;
- OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, sys::fs::F_Append);
+ OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
+ sys::fs::F_Append | sys::fs::F_Text);
if (!ErrorInfo.empty()) {
errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
exit(1);
TRI = TM->getRegisterInfo();
MRI = &MF.getRegInfo();
- LiveVars = NULL;
- LiveInts = NULL;
- LiveStks = NULL;
- Indexes = NULL;
+ LiveVars = nullptr;
+ LiveInts = nullptr;
+ LiveStks = nullptr;
+ Indexes = nullptr;
if (PASS) {
LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
// We don't want to verify LiveVariables if LiveIntervals is available.
MFI!=MFE; ++MFI) {
visitMachineBasicBlockBefore(MFI);
// Keep track of the current bundle header.
- const MachineInstr *CurBundle = 0;
+ const MachineInstr *CurBundle = nullptr;
// Do we expect the next instruction to be part of the same bundle?
bool InBundle = false;
void
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
- FirstTerminator = 0;
+ FirstTerminator = nullptr;
if (MRI->isSSA()) {
// If this block has allocatable physical registers live-in, check that
report("MBB has more than one landing pad successor", MBB);
// Call AnalyzeBranch. If it succeeds, there several more conditions to check.
- MachineBasicBlock *TBB = 0, *FBB = 0;
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
TBB, FBB, Cond)) {
// Verify SSA form.
if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
- llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
+ std::next(MRI->def_begin(Reg)) != MRI->def_end())
report("Multiple virtual register defs in SSA form", MO, MONum);
// Check LiveInts for a live segment, but only for virtual registers.