MachineVerifier(Pass *pass, bool allowDoubleDefs) :
PASS(pass),
allowVirtDoubleDefs(allowDoubleDefs),
- allowPhysDoubleDefs(allowDoubleDefs),
+ allowPhysDoubleDefs(true),
OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
{}
void report(const char *msg, const MachineOperand *MO, unsigned MONum);
void markReachable(const MachineBasicBlock *MBB);
- void calcMaxRegsPassed();
- void calcMinRegsPassed();
+ void calcRegsPassed();
void checkPHIOps(const MachineBasicBlock *MBB);
void calcRegsRequired();
if (OutFile)
delete OutFile;
else if (foundErrors)
- llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
+ report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
// Clean up.
regsLive.clear();
}
// Does iterator point to a and b as the first two elements?
-bool matchPair(MachineBasicBlock::const_succ_iterator i,
- const MachineBasicBlock *a, const MachineBasicBlock *b) {
+static bool matchPair(MachineBasicBlock::const_succ_iterator i,
+ const MachineBasicBlock *a, const MachineBasicBlock *b) {
if (*i == a)
return *++i == b;
if (*i == b)
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
- // Start with minimal CFG sanity checks.
- MachineFunction::const_iterator MBBI = MBB;
- ++MBBI;
- if (MBBI != MF->end()) {
- // Block is not last in function.
- if (!MBB->isSuccessor(MBBI)) {
- // Block does not fall through.
- if (MBB->empty()) {
- report("MBB doesn't fall through but is empty!", MBB);
- }
- }
- } else {
- // Block is last in function.
- if (MBB->empty()) {
- report("MBB is last in function but is empty!", MBB);
- }
- }
-
// Call AnalyzeBranch. If it succeeds, there several more conditions to check.
MachineBasicBlock *TBB = 0, *FBB = 0;
SmallVector<MachineOperand, 4> Cond;
}
regsLive.clear();
- for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
+ for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I) {
if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
report("MBB live-in list contains non-physical register", MBB);
report("Explicit operand marked as implicit", MO, MONum);
}
} else {
- if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
+ // ARM adds %reg0 operands to indicate predicates. We'll allow that.
+ if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
report("Extra explicit operand on non-variadic instruction", MO, MONum);
}
regsLiveInButUnused.erase(Reg);
bool isKill = false;
- if (MO->isKill()) {
- isKill = true;
- // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
- if (MI->isRegTiedToDefOperand(MONum))
+ unsigned defIdx;
+ if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
+ // A two-addr use counts as a kill if use and def are the same.
+ unsigned DefReg = MI->getOperand(defIdx).getReg();
+ if (Reg == DefReg) {
+ isKill = true;
+ // ANd in that case an explicit kill flag is not allowed.
+ if (MO->isKill())
report("Illegal kill flag on two-address instruction operand",
MO, MONum);
- } else {
- // TwoAddress instr modifying a reg is treated as kill+def.
- unsigned defIdx;
- if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
- MI->getOperand(defIdx).getReg() == Reg)
- isKill = true;
- }
+ } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ report("Two-address instruction operands must be identical",
+ MO, MONum);
+ }
+ } else
+ isKill = MO->isKill();
+
if (isKill) {
addRegWithSubRegs(regsKilled, Reg);
// must be live in. PHI instructions are handled separately.
if (MInfo.regsKilled.count(Reg))
report("Using a killed virtual register", MO, MONum);
- else if (MI->getOpcode() != TargetInstrInfo::PHI)
+ else if (!MI->isPHI())
MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
}
}
// Virtual register.
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
if (SubIdx) {
- if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
+ const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
+ if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
+ *OS << "Register class " << RC->getName()
+ << " does not support subreg index " << SubIdx << "\n";
return;
}
- RC = *(RC->subregclasses_begin()+SubIdx);
+ RC = SRC;
}
if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
if (RC != DRC && !RC->hasSuperClass(DRC)) {
}
case MachineOperand::MO_MachineBasicBlock:
- if (MI->getOpcode() == TargetInstrInfo::PHI) {
- if (!MO->getMBB()->isSuccessor(MI->getParent()))
- report("PHI operand is not in the CFG", MO, MONum);
- }
+ if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
+ report("PHI operand is not in the CFG", MO, MONum);
break;
default:
// Calculate the largest possible vregsPassed sets. These are the registers that
// can pass through an MBB live, but may not be live every time. It is assumed
// that all vregsPassed sets are empty before the call.
-void MachineVerifier::calcMaxRegsPassed() {
+void MachineVerifier::calcRegsPassed() {
// First push live-out regs to successors' vregsPassed. Remember the MBBs that
// have any vregsPassed.
DenseSet<const MachineBasicBlock*> todo;
}
}
-// Calculate the minimum vregsPassed set. These are the registers that always
-// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
-// been called earlier.
-void MachineVerifier::calcMinRegsPassed() {
- DenseSet<const MachineBasicBlock*> todo;
- for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
- MFI != MFE; ++MFI)
- todo.insert(MFI);
-
- while (!todo.empty()) {
- const MachineBasicBlock *MBB = *todo.begin();
- todo.erase(MBB);
- BBInfo &MInfo = MBBInfoMap[MBB];
-
- // Remove entries from vRegsPassed that are not live out from all
- // reachable predecessors.
- RegSet dead;
- for (RegSet::iterator I = MInfo.vregsPassed.begin(),
- E = MInfo.vregsPassed.end(); I != E; ++I) {
- for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
- PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
- BBInfo &PrInfo = MBBInfoMap[*PrI];
- if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
- dead.insert(*I);
- break;
- }
- }
- }
- // If any regs removed, we need to recheck successors.
- if (!dead.empty()) {
- set_subtract(MInfo.vregsPassed, dead);
- todo.insert(MBB->succ_begin(), MBB->succ_end());
- }
- }
-}
-
// Calculate the set of virtual registers that must be passed through each basic
// block in order to satisfy the requirements of successor blocks. This is very
-// similar to calcMaxRegsPassed, only backwards.
+// similar to calcRegsPassed, only backwards.
void MachineVerifier::calcRegsRequired() {
// First push live-in regs to predecessors' vregsRequired.
DenseSet<const MachineBasicBlock*> todo;
}
// Check PHI instructions at the beginning of MBB. It is assumed that
-// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
+// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
- BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
+ BBI != BBE && BBI->isPHI(); ++BBI) {
DenseSet<const MachineBasicBlock*> seen;
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
}
void MachineVerifier::visitMachineFunctionAfter() {
- calcMaxRegsPassed();
+ calcRegsPassed();
- // With the maximal set of vregsPassed we can verify dead-in registers.
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
MFI != MFE; ++MFI) {
BBInfo &MInfo = MBBInfoMap[MFI];
if (!MInfo.reachable)
continue;
- for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
- PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
- BBInfo &PrInfo = MBBInfoMap[*PrI];
- if (!PrInfo.reachable)
- continue;
-
- // Verify physical live-ins. EH landing pads have magic live-ins so we
- // ignore them.
- if (!MFI->isLandingPad()) {
- for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
- E = MFI->livein_end(); I != E; ++I) {
- if (TargetRegisterInfo::isPhysicalRegister(*I) &&
- !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
- report("Live-in physical register is not live-out from predecessor",
- MFI);
- *OS << "Register " << TRI->getName(*I)
- << " is not live-out from BB#" << (*PrI)->getNumber()
- << ".\n";
- }
- }
- }
+ checkPHIOps(MFI);
+ // Verify dead-in virtual registers.
+ if (!allowVirtDoubleDefs) {
+ for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
+ PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
+ BBInfo &PrInfo = MBBInfoMap[*PrI];
+ if (!PrInfo.reachable)
+ continue;
- // Verify dead-in virtual registers.
- if (!allowVirtDoubleDefs) {
for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
E = MInfo.vregsDeadIn.end(); I != E; ++I) {
// DeadIn register must be in neither regsLiveOut or vregsPassed of
}
}
- calcMinRegsPassed();
-
- // With the minimal set of vregsPassed we can verify live-in virtual
- // registers, including PHI instructions.
- for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
- MFI != MFE; ++MFI) {
- BBInfo &MInfo = MBBInfoMap[MFI];
-
- // Skip unreachable MBBs.
- if (!MInfo.reachable)
- continue;
-
- checkPHIOps(MFI);
-
- for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
- PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
- BBInfo &PrInfo = MBBInfoMap[*PrI];
- if (!PrInfo.reachable)
- continue;
-
- for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
- E = MInfo.vregsLiveIn.end(); I != E; ++I) {
- if (!PrInfo.isLiveOut(I->first)) {
- report("Used virtual register is not live-in", I->second);
- *OS << "Register %reg" << I->first
- << " is not live-out from predecessor MBB #"
- << (*PrI)->getNumber()
- << ".\n";
- }
- }
- }
- }
-
// Now check LiveVariables info if available
if (LiveVars) {
calcRegsRequired();
projects / oota-llvm.git / blobdiff