Merge vector stores into wider vector stores (PR21711)

[oota-llvm.git] / lib / CodeGen / MachineVerifier.cpp

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 677b5093f40a951476c3513300047c327dec4c18..88bd193d0c3382e7790e3b11bc62f4ce763e4cd9 100644 (file)
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -243,10 +243,10 @@ namespace {
 
   struct MachineVerifierPass : public MachineFunctionPass {
     static char ID; // Pass ID, replacement for typeid
-    const char *const Banner;
+    const std::string Banner;
 
-    MachineVerifierPass(const char *b = nullptr)
-      : MachineFunctionPass(ID), Banner(b) {
+    MachineVerifierPass(const std::string &banner = nullptr)
+      : MachineFunctionPass(ID), Banner(banner) {
         initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
       }
 
@@ -256,7 +256,7 @@ namespace {
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
-      MF.verify(this, Banner);
+      MF.verify(this, Banner.c_str());
       return false;
     }
   };
@@ -267,7 +267,7 @@ char MachineVerifierPass::ID = 0;
 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
                 "Verify generated machine code", false, false)
 
-FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
+FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
   return new MachineVerifierPass(Banner);
 }
 
@@ -1077,6 +1077,25 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
             }
           }
         }
+        // If there is an additional implicit-use of a super register we stop
+        // here. By definition we are fine if the super register is not
+        // (completely) dead, if the complete super register is dead we will
+        // get a report for its operand.
+        if (Bad) {
+          for (const MachineOperand &MOP : MI->uses()) {
+            if (!MOP.isReg())
+              continue;
+            if (!MOP.isImplicit())
+              continue;
+            for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
+                 ++SubRegs) {
+              if (*SubRegs == Reg) {
+                Bad = false;
+                break;
+              }
+            }
+          }
+        }
         if (Bad)
           report("Using an undefined physical register", MO, MONum);
       } else if (MRI->def_empty(Reg)) {
@@ -1643,9 +1662,8 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
 
 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
                                       unsigned LaneMask) {
-  for (LiveRange::const_vni_iterator I = LR.vni_begin(), E = LR.vni_end();
-       I != E; ++I)
-    verifyLiveRangeValue(LR, *I, Reg, LaneMask);
+  for (const VNInfo *VNI : LR.valnos)
+    verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
 
   for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
     verifyLiveRangeSegment(LR, I, Reg, LaneMask);
@@ -1658,15 +1676,14 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     unsigned Mask = 0;
     unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
-    for (LiveInterval::const_subrange_iterator I = LI.subrange_begin(),
-         E = LI.subrange_end(); I != E; ++I) {
-      if ((Mask & I->LaneMask) != 0)
+    for (const LiveInterval::SubRange &SR : LI.subranges()) {
+      if ((Mask & SR.LaneMask) != 0)
         report("Lane masks of sub ranges overlap in live interval", MF, LI);
-      if ((I->LaneMask & ~MaxMask) != 0)
+      if ((SR.LaneMask & ~MaxMask) != 0)
         report("Subrange lanemask is invalid", MF, LI);
-      Mask |= I->LaneMask;
-      verifyLiveRange(*I, LI.reg, I->LaneMask);
-      if (!LI.covers(*I))
+      Mask |= SR.LaneMask;
+      verifyLiveRange(SR, LI.reg, SR.LaneMask);
+      if (!LI.covers(SR))
         report("A Subrange is not covered by the main range", MF, LI);
     }
   } else if (LI.hasSubRanges()) {