[DAG] Check in advance if a build_vector has a legal type before attempting to conver...
[oota-llvm.git] / lib / CodeGen / MachineLICM.cpp
index 8960d38e61061eeb74b53452569b868610fed360..ce69cc5b9debfdbd67db508492f59b41febd8362 100644 (file)
@@ -20,7 +20,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "machine-licm"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "machine-licm"
+
 static cl::opt<bool>
 AvoidSpeculation("avoid-speculation",
                  cl::desc("MachineLICM should avoid speculation"),
@@ -324,12 +326,12 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
 
   Changed = FirstInLoop = false;
   TM = &MF.getTarget();
-  TII = TM->getInstrInfo();
-  TLI = TM->getTargetLowering();
-  TRI = TM->getRegisterInfo();
+  TII = TM->getSubtargetImpl()->getInstrInfo();
+  TLI = TM->getSubtargetImpl()->getTargetLowering();
+  TRI = TM->getSubtargetImpl()->getRegisterInfo();
   MFI = MF.getFrameInfo();
   MRI = &MF.getRegInfo();
-  InstrItins = TM->getInstrItineraryData();
+  InstrItins = TM->getSubtargetImpl()->getInstrItineraryData();
 
   PreRegAlloc = MRI->isSSA();
 
@@ -1038,7 +1040,7 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
 /// the operand latency between its def and a use is one or less.
 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
-  if (MI.isAsCheapAsAMove() || MI.isCopyLike())
+  if (TII->isAsCheapAsAMove(&MI) || MI.isCopyLike())
     return true;
   if (!InstrItins || InstrItins->isEmpty())
     return false;