Handle load/store of misaligned vectors that are the

[oota-llvm.git] / lib / CodeGen / MachineLICM.cpp

diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 94e10611226d84e7535fd0fd064edc46b82bb5dd..89ab93df0a63b133b905419145069041e38ee850 100644 (file)
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -17,7 +17,7 @@
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
@@ -223,30 +223,48 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
 /// effects that aren't captured by the operands or other flags.
 /// 
 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
+  const TargetInstrDesc &TID = I.getDesc();
+  
+  // Ignore stuff that we obviously can't hoist.
+  if (TID.mayStore() || TID.isCall() || TID.isReturn() || TID.isBranch() ||
+      TID.hasUnmodeledSideEffects())
+    return false;
+  
+  if (TID.mayLoad()) {
+    // Okay, this instruction does a load.  As a refinement, allow the target
+    // to decide whether the loaded value is actually a constant.  If so, we
+    // can actually use it as a load.
+    if (!TII->isInvariantLoad(&I)) {
+      // FIXME: we should be able to sink loads with no other side effects if
+      // there is nothing that can change memory from here until the end of
+      // block.  This is a trivial form of alias analysis.
+      return false;
+    }
+  }
+  
+  
   DEBUG({
       DOUT << "--- Checking if we can hoist " << I;
-      if (I.getInstrDescriptor()->ImplicitUses) {
+      if (I.getDesc().getImplicitUses()) {
         DOUT << "  * Instruction has implicit uses:\n";
 
-        const MRegisterInfo *MRI = TM->getRegisterInfo();
-        const unsigned *ImpUses = I.getInstrDescriptor()->ImplicitUses;
-
-        for (; *ImpUses; ++ImpUses)
-          DOUT << "      -> " << MRI->getName(*ImpUses) << "\n";
+        const TargetRegisterInfo *TRI = TM->getRegisterInfo();
+        for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
+             *ImpUses; ++ImpUses)
+          DOUT << "      -> " << TRI->getName(*ImpUses) << "\n";
       }
 
-      if (I.getInstrDescriptor()->ImplicitDefs) {
+      if (I.getDesc().getImplicitDefs()) {
         DOUT << "  * Instruction has implicit defines:\n";
 
-        const MRegisterInfo *MRI = TM->getRegisterInfo();
-        const unsigned *ImpDefs = I.getInstrDescriptor()->ImplicitDefs;
-
-        for (; *ImpDefs; ++ImpDefs)
-          DOUT << "      -> " << MRI->getName(*ImpDefs) << "\n";
+        const TargetRegisterInfo *TRI = TM->getRegisterInfo();
+        for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
+             *ImpDefs; ++ImpDefs)
+          DOUT << "      -> " << TRI->getName(*ImpDefs) << "\n";
       }
 
-      if (TII->hasUnmodelledSideEffects(&I))
-        DOUT << "  * Instruction has side effects.\n";
+        //if (TII->hasUnmodelledSideEffects(&I))
+        //DOUT << "  * Instruction has side effects.\n";
     });
 
   // The instruction is loop invariant if all of its operands are loop-invariant
@@ -259,7 +277,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
     unsigned Reg = MO.getReg();
 
     // Don't hoist instructions that access physical registers.
-    if (!MRegisterInfo::isVirtualRegister(Reg))
+    if (!TargetRegisterInfo::isVirtualRegister(Reg))
       return false;
 
     assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?");
@@ -270,9 +288,6 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
       return false;
   }
 
-  // Don't hoist something that has unmodelled side effects.
-  if (TII->hasUnmodelledSideEffects(&I)) return false;
-
   // If we got this far, the instruction is loop invariant!
   return true;
 }