//
//===----------------------------------------------------------------------===//
+#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Value.h"
#include "llvm/CodeGen/MachineFunction.h"
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
+ case MachineOperand::MO_FPImmediate:
+ return getFPImm() == Other.getFPImm();
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
NeedComma = true;
}
if (isKill() || isDead()) {
- if (NeedComma) OS << ",";
- if (isKill()) OS << "kill";
- if (isDead()) OS << "dead";
+ if (NeedComma) OS << ",";
+ if (isKill()) OS << "kill";
+ if (isDead()) OS << "dead";
}
OS << ">";
}
case MachineOperand::MO_Immediate:
OS << getImm();
break;
+ case MachineOperand::MO_FPImmediate:
+ if (getFPImm()->getType() == Type::FloatTy) {
+ OS << getFPImm()->getValueAPF().convertToFloat();
+ } else {
+ OS << getFPImm()->getValueAPF().convertToDouble();
+ }
+ break;
case MachineOperand::MO_MachineBasicBlock:
OS << "mbb<"
<< ((Value*)getMBB()->getBasicBlock())->getName()
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
-int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
+int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
+ const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
+ if (!MO.isRegister() || !MO.isUse())
+ continue;
+ unsigned MOReg = MO.getReg();
+ if (!MOReg)
+ continue;
+ if (MOReg == Reg ||
+ (TRI &&
+ TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TRI->isSubRegister(MOReg, Reg)))
if (!isKill || MO.isKill())
return i;
}
return -1;
}
-/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
-/// the specific register or NULL if it is not found.
-MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
+/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
+/// the specified register or -1 if it is not found. If isDead is true, defs
+/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
+/// also checks if there is a def of a super-register.
+int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
+ const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
- MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
- return &MO;
+ const MachineOperand &MO = getOperand(i);
+ if (!MO.isRegister() || !MO.isDef())
+ continue;
+ unsigned MOReg = MO.getReg();
+ if (MOReg == Reg ||
+ (TRI &&
+ TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TRI->isSubRegister(MOReg, Reg)))
+ if (!isDead || MO.isDead())
+ return i;
}
- return NULL;
+ return -1;
}
/// findFirstPredOperandIdx() - Find the index of the first operand in the
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
const TargetInstrDesc &TID = MI->getDesc();
- if (TID.isPredicable()) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if (TID.OpInfo[i].isPredicate()) {
- // Predicated operands must be last operands.
- addOperand(MI->getOperand(i));
- }
+ if (!TID.isPredicable())
+ return;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if (TID.OpInfo[i].isPredicate()) {
+ // Predicated operands must be last operands.
+ addOperand(MI->getOperand(i));
}
}
}
+/// isSafeToMove - Return true if it is safe to this instruction. If SawStore is
+/// set to true, it means that there is a store (or call) between the
+/// instruction's location and its intended destination.
+bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
+ // Ignore stuff that we obviously can't move.
+ if (TID->mayStore() || TID->isCall()) {
+ SawStore = true;
+ return false;
+ }
+ if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
+ return false;
+
+ // See if this instruction does a load. If so, we have to guarantee that the
+ // loaded value doesn't change between the load and the its intended
+ // destination. The check for isInvariantLoad gives the targe the chance to
+ // classify the load as always returning a constant, e.g. a constant pool
+ // load.
+ if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
+ // Otherwise, this is a real load. If there is a store between the load and
+ // end of block, we can't sink the load.
+ //
+ // FIXME: we can't do this transformation until we know that the load is
+ // not volatile, and machineinstrs don't keep this info. :(
+ //
+ //if (SawStore)
+ return false;
+ }
+ return true;
+}
+
void MachineInstr::dump() const {
cerr << " " << *this;
}
if (getNumMemOperands() > 0) {
OS << ", Mem:";
for (unsigned i = 0; i < getNumMemOperands(); i++) {
- const MemOperand &MRO = getMemOperand(i);
+ const MachineMemOperand &MRO = getMemOperand(i);
const Value *V = MRO.getValue();
assert((MRO.isLoad() || MRO.isStore()) &&
bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
bool Found = false;
+ SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isUse()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
+ if (!MO.isRegister() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+
+ if (Reg == IncomingReg) {
+ if (!Found) // One kill of reg per instruction.
MO.setIsKill();
+ Found = true;
+ } else if (isPhysReg && MO.isKill() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ // A super-register kill already exists.
+ if (RegInfo->isSuperRegister(IncomingReg, Reg))
Found = true;
- break;
- } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
- TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isKill())
- // A super-register kill already exists.
- Found = true;
+ else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ DeadOps.push_back(i);
}
}
- // If not found, this means an alias of one of the operand is killed. Add a
+ // Trim unneeded kill operands.
+ while (!DeadOps.empty()) {
+ unsigned OpIdx = DeadOps.back();
+ if (getOperand(OpIdx).isImplicit())
+ RemoveOperand(OpIdx);
+ else
+ getOperand(OpIdx).setIsKill(false);
+ DeadOps.pop_back();
+ }
+
+ // If not found, this means an alias of one of the operands is killed. Add a
// new implicit operand if required.
if (!Found && AddIfNotFound) {
- addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
- true/*IsImp*/,true/*IsKill*/));
+ addOperand(MachineOperand::CreateReg(IncomingReg,
+ false /*IsDef*/,
+ true /*IsImp*/,
+ true /*IsKill*/));
return true;
}
return Found;
bool MachineInstr::addRegisterDead(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
bool Found = false;
+ SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isDef()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
- MO.setIsDead();
+ if (!MO.isRegister() || !MO.isDef())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == IncomingReg) {
+ MO.setIsDead();
+ Found = true;
+ } else if (isPhysReg && MO.isDead() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ // There exists a super-register that's marked dead.
+ if (RegInfo->isSuperRegister(IncomingReg, Reg))
Found = true;
- break;
- } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
- TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isDead())
- // There exists a super-register that's marked dead.
- return true;
+ else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ DeadOps.push_back(i);
}
}
+ // Trim unneeded dead operands.
+ while (!DeadOps.empty()) {
+ unsigned OpIdx = DeadOps.back();
+ if (getOperand(OpIdx).isImplicit())
+ RemoveOperand(OpIdx);
+ else
+ getOperand(OpIdx).setIsDead(false);
+ DeadOps.pop_back();
+ }
+
// If not found, this means an alias of one of the operand is dead. Add a
// new implicit operand.
if (!Found && AddIfNotFound) {
projects / oota-llvm.git / blobdiff