Preliminary PIC JIT support for X86 (32-bit) / Darwin.

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 9d09a9f95e54b11d3e89e2d694a4d1c7ce7138be..c5145ff1809e82ac77bce7aee4f91989a92a0175 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -60,16 +60,17 @@ void MachineInstr::addImplicitDefUseOperands() {
 /// implicit operands. It reserves space for number of operands specified by
 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
 /// instructions with variable number of operands).
-MachineInstr::MachineInstr(const TargetInstrDescriptor &tid)
+MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
   : TID(&tid), NumImplicitOps(0), parent(0) {
-  if (TID->ImplicitDefs)
+  if (!NoImp && TID->ImplicitDefs)
     for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
       NumImplicitOps++;
-  if (TID->ImplicitUses)
+  if (!NoImp && TID->ImplicitUses)
     for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
       NumImplicitOps++;
   Operands.reserve(NumImplicitOps + TID->numOperands);
-  addImplicitDefUseOperands();
+  if (!NoImp)
+    addImplicitDefUseOperands();
   // Make sure that we get added to a machine basicblock
   LeakDetector::addGarbageObject(this);
 }
@@ -118,7 +119,7 @@ MachineInstr::~MachineInstr() {
 
 /// getOpcode - Returns the opcode of this MachineInstr.
 ///
-const int MachineInstr::getOpcode() const {
+int MachineInstr::getOpcode() const {
   return TID->Opcode;
 }
 
@@ -141,6 +142,21 @@ bool MachineInstr::OperandsComplete() const {
   return false;
 }
 
+/// getNumExplicitOperands - Returns the number of non-implicit operands.
+///
+unsigned MachineInstr::getNumExplicitOperands() const {
+  unsigned NumOperands = TID->numOperands;
+  if ((TID->Flags & M_VARIABLE_OPS) == 0)
+    return NumOperands;
+
+  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
+    const MachineOperand &MO = getOperand(NumOperands);
+    if (!MO.isRegister() || !MO.isImplicit())
+      NumOperands++;
+  }
+  return NumOperands;
+}
+
 /// isIdenticalTo - Return true if this operand is identical to the specified
 /// operand.
 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
@@ -172,10 +188,10 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
 /// the specific register or -1 if it is not found. It further tightening
 /// the search criteria to a use that kills the register if isKill is true.
-int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) {
+int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = getOperand(i);
-    if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
+    const MachineOperand &MO = getOperand(i);
+    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
       if (!isKill || MO.isKill())
         return i;
   }
@@ -187,18 +203,50 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) {
 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     MachineOperand &MO = getOperand(i);
-    if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
       return &MO;
   }
   return NULL;
 }
+
+/// findFirstPredOperandIdx() - Find the index of the first operand in the
+/// operand list that is used to represent the predicate. It returns -1 if
+/// none is found.
+int MachineInstr::findFirstPredOperandIdx() const {
+  const TargetInstrDescriptor *TID = getInstrDescriptor();
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+        return i;
+  }
+
+  return -1;
+}
   
+/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
+/// to two addr elimination.
+bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
+  const TargetInstrDescriptor *TID = getInstrDescriptor();
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO1 = getOperand(i);
+    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
+      for (unsigned j = i+1; j < e; ++j) {
+        const MachineOperand &MO2 = getOperand(j);
+        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
+            TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
+          return true;
+      }
+    }
+  }
+  return false;
+}
+
 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
 ///
 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
+    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
       continue;
     for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
       MachineOperand &MOp = getOperand(j);
@@ -213,6 +261,24 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
   }
 }
 
+/// copyPredicates - Copies predicate operand(s) from MI.
+void MachineInstr::copyPredicates(const MachineInstr *MI) {
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+        const MachineOperand &MO = MI->getOperand(i);
+        // Predicated operands must be last operands.
+        if (MO.isRegister())
+          addRegOperand(MO.getReg(), false);
+        else {
+          addImmOperand(MO.getImm());
+        }
+      }
+    }
+  }
+}
+
 void MachineInstr::dump() const {
   cerr << "  " << *this;
 }
@@ -274,7 +340,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
   unsigned StartOp = 0;
 
    // Specialize printing if op#0 is definition
-  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
+  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
     ::print(getOperand(0), OS, TM);
     if (getOperand(0).isDead())
       OS << "<dead>";
@@ -292,7 +358,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
     OS << " ";
     ::print(mop, OS, TM);
 
-    if (mop.isReg()) {
+    if (mop.isRegister()) {
       if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
         OS << "<";
         bool NeedComma = false;
@@ -336,7 +402,7 @@ void MachineInstr::print(std::ostream &os) const {
 
   for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
     os << "\t" << getOperand(i);
-    if (getOperand(i).isReg() && getOperand(i).isDef())
+    if (getOperand(i).isRegister() && getOperand(i).isDef())
       os << "<d>";
   }