-// $Id$
-//***************************************************************************
-// File:
-// MachineInstr.cpp
+//===-- MachineInstr.cpp --------------------------------------------------===//
//
-// Purpose:
-//
-//
-// Strategy:
-//
-// History:
-// 7/2/01 - Vikram Adve - Created
-//**************************************************************************/
+//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/ConstPoolVals.h"
-#include "llvm/Instruction.h"
-#include <strstream>
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/Value.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/MRegisterInfo.h"
-//************************ Class Implementations **************************/
+// Global variable holding an array of descriptors for machine instructions.
+// The actual object needs to be created separately for each target machine.
+// This variable is initialized and reset by class TargetInstrInfo.
+//
+// FIXME: This should be a property of the target so that more than one target
+// at a time can be active...
+//
+extern const TargetInstrDescriptor *TargetInstrDescriptors;
+// Constructor for instructions with variable #operands
+MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
+ : opCode(OpCode),
+ opCodeFlags(0),
+ operands(numOperands, MachineOperand()),
+ numImplicitRefs(0)
+{
+}
-bool
-MachineInstrInfo::constantFitsInImmedField(int64_t intValue) const
+/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
+/// not a resize for them. It is expected that if you use this that you call
+/// add* methods below to fill up the operands, instead of the Set methods.
+/// Eventually, the "resizing" ctors will be phased out.
+///
+MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
+ bool XX, bool YY)
+ : opCode(Opcode),
+ opCodeFlags(0),
+ numImplicitRefs(0)
{
- // First, check if opCode has an immed field.
- bool isSignExtended;
- uint64_t maxImmedValue = this->maxImmedConstant(isSignExtended);
- if (maxImmedValue != 0)
- {
- // Now check if the constant fits
- if (intValue <= (int64_t) maxImmedValue &&
- intValue >= -((int64_t) maxImmedValue+1))
- return true;
- }
-
- return false;
+ operands.reserve(numOperands);
}
-MachineInstr::MachineInstr(MachineOpCode _opCode,
- OpCodeMask _opCodeMask)
- : opCode(_opCode),
- opCodeMask(_opCodeMask),
- operands(TargetMachineInstrInfo[_opCode].numOperands)
+/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
+/// MachineInstr is created and added to the end of the specified basic block.
+///
+MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
+ unsigned numOperands)
+ : opCode(Opcode),
+ opCodeFlags(0),
+ numImplicitRefs(0)
{
+ assert(MBB && "Cannot use inserting ctor with null basic block!");
+ operands.reserve(numOperands);
+ MBB->push_back(this); // Add instruction to end of basic block!
}
-MachineInstr::~MachineInstr()
+
+// OperandComplete - Return true if it's illegal to add a new operand
+bool MachineInstr::OperandsComplete() const
{
+ int NumOperands = TargetInstrDescriptors[opCode].numOperands;
+ if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
+ return true; // Broken: we have all the operands of this instruction!
+ return false;
}
-void
-MachineInstr::SetMachineOperand(unsigned int i,
- MachineOperand::MachineOperandType operandType,
- Value* _val)
+
+//
+// Support for replacing opcode and operands of a MachineInstr in place.
+// This only resets the size of the operand vector and initializes it.
+// The new operands must be set explicitly later.
+//
+void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
{
- assert(i < TargetMachineInstrInfo[opCode].numOperands);
- operands[i].Initialize(operandType, _val);
+ assert(getNumImplicitRefs() == 0 &&
+ "This is probably broken because implicit refs are going to be lost.");
+ opCode = Opcode;
+ operands.clear();
+ operands.resize(numOperands, MachineOperand());
+}
+
+void MachineInstr::SetMachineOperandVal(unsigned i,
+ MachineOperand::MachineOperandType opTy,
+ Value* V) {
+ assert(i < operands.size()); // may be explicit or implicit op
+ operands[i].opType = opTy;
+ operands[i].value = V;
+ operands[i].regNum = -1;
}
void
-MachineInstr::SetMachineOperand(unsigned int i,
+MachineInstr::SetMachineOperandConst(unsigned i,
MachineOperand::MachineOperandType operandType,
- int64_t intValue)
+ int64_t intValue)
{
- assert(i < TargetMachineInstrInfo[opCode].numOperands);
- operands[i].InitializeConst(operandType, intValue);
+ assert(i < getNumOperands()); // must be explicit op
+ assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
+ "immed. constant cannot be defined");
+
+ operands[i].opType = operandType;
+ operands[i].value = NULL;
+ operands[i].immedVal = intValue;
+ operands[i].regNum = -1;
+ operands[i].flags = 0;
+}
+
+void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
+ assert(i < getNumOperands()); // must be explicit op
+
+ operands[i].opType = MachineOperand::MO_MachineRegister;
+ operands[i].value = NULL;
+ operands[i].regNum = regNum;
}
void
-MachineInstr::SetMachineOperand(unsigned int i,
- unsigned int regNum)
+MachineInstr::SetRegForOperand(unsigned i, int regNum)
{
- assert(i < TargetMachineInstrInfo[opCode].numOperands);
- operands[i].InitializeReg(regNum);
+ assert(i < getNumOperands()); // must be explicit op
+ operands[i].setRegForValue(regNum);
}
void
-MachineInstr::dump(unsigned int indent)
+MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
{
- for (unsigned i=0; i < indent; i++)
- cout << " ";
-
- cout << *this;
+ getImplicitOp(i).setRegForValue(regNum);
}
-ostream&
-operator<< (ostream& os, const MachineInstr& minstr)
+
+// Subsitute all occurrences of Value* oldVal with newVal in all operands
+// and all implicit refs.
+// If defsOnly == true, substitute defs only.
+unsigned
+MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
+ bool defsOnly, bool notDefsAndUses,
+ bool& someArgsWereIgnored)
{
- os << TargetMachineInstrInfo[minstr.opCode].opCodeString;
-
- for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++)
- os << "\t" << minstr.getOperand(i);
+ assert((!defsOnly || !notDefsAndUses) &&
+ "notDefsAndUses is irrelevant if defsOnly == true.");
- return os;
-}
+ unsigned numSubst = 0;
-ostream&
-operator<< (ostream& os, const MachineOperand& mop)
-{
- strstream regInfo;
- if (mop.machineOperandType == MachineOperand::MO_Register)
- {
- if (mop.vregType == MachineOperand::MO_VirtualReg)
- regInfo << "(val " << mop.value << ")" << ends;
+ // Subsitute operands
+ for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
+ if (*O == oldVal)
+ if (!defsOnly ||
+ notDefsAndUses && O.isDefOnly() ||
+ !notDefsAndUses && !O.isUseOnly())
+ {
+ O.getMachineOperand().value = newVal;
+ ++numSubst;
+ }
else
- regInfo << "(" << mop.regNum << ")" << ends;
- }
- else if (mop.machineOperandType == MachineOperand::MO_CCRegister)
- regInfo << "(val " << mop.value << ")" << ends;
-
- switch(mop.machineOperandType)
- {
- case MachineOperand::MO_Register:
- os << "%reg" << regInfo.str();
- free(regInfo.str());
- break;
-
- case MachineOperand::MO_CCRegister:
- os << "%ccreg" << regInfo.str();
- free(regInfo.str());
- break;
+ someArgsWereIgnored = true;
- case MachineOperand::MO_SignExtendedImmed:
- os << mop.immedVal;
- break;
+ // Subsitute implicit refs
+ for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
+ if (getImplicitRef(i) == oldVal)
+ if (!defsOnly ||
+ notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
+ !notDefsAndUses && !getImplicitOp(i).opIsUse())
+ {
+ getImplicitOp(i).value = newVal;
+ ++numSubst;
+ }
+ else
+ someArgsWereIgnored = true;
- case MachineOperand::MO_UnextendedImmed:
- os << mop.immedVal;
- break;
+ return numSubst;
+}
- case MachineOperand::MO_PCRelativeDisp:
- os << "%disp(label " << mop.value << ")";
- break;
- default:
- assert(0 && "Unrecognized operand type");
- break;
- }
+void
+MachineInstr::dump() const
+{
+ std::cerr << " " << *this;
+}
+static inline std::ostream&
+OutputValue(std::ostream &os, const Value* val)
+{
+ os << "(val ";
+ os << (void*) val; // print address always
+ if (val && val->hasName())
+ os << " " << val->getName() << ")"; // print name also, if available
return os;
}
+static inline void OutputReg(std::ostream &os, unsigned RegNo,
+ const MRegisterInfo *MRI = 0) {
+ if (MRI) {
+ if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ os << "%" << MRI->get(RegNo).Name;
+ else
+ os << "%reg" << RegNo;
+ } else
+ os << "%mreg(" << RegNo << ")";
+}
-//---------------------------------------------------------------------------
-// Target-independent utility routines for creating machine instructions
-//---------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------
-// Function Set2OperandsFromInstr
-// Function Set3OperandsFromInstr
-//
-// For the common case of 2- and 3-operand arithmetic/logical instructions,
-// set the m/c instr. operands directly from the VM instruction's operands.
-// Check whether the first or second operand is 0 and can use a dedicated "0" register.
-// Check whether the second operand should use an immediate field or register.
-// (First and third operands are never immediates for such instructions.)
-//
-// Arguments:
-// canDiscardResult: Specifies that the result operand can be discarded
-// by using the dedicated "0"
-//
-// op1position, op2position and resultPosition: Specify in which position
-// in the machine instruction the 3 operands (arg1, arg2
-// and result) should go.
-//
-// RETURN VALUE: unsigned int flags, where
-// flags & 0x01 => operand 1 is constant and needs a register
-// flags & 0x02 => operand 2 is constant and needs a register
-//------------------------------------------------------------------------
+static void print(const MachineOperand &MO, std::ostream &OS,
+ const TargetMachine &TM) {
+ const MRegisterInfo *MRI = TM.getRegisterInfo();
+ bool CloseParen = true;
+ if (MO.opHiBits32())
+ OS << "%lm(";
+ else if (MO.opLoBits32())
+ OS << "%lo(";
+ else if (MO.opHiBits64())
+ OS << "%hh(";
+ else if (MO.opLoBits64())
+ OS << "%hm(";
+ else
+ CloseParen = false;
+
+ switch (MO.getType()) {
+ case MachineOperand::MO_VirtualRegister:
+ if (MO.getVRegValue()) {
+ OS << "%reg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg())
+ OS << "==";
+ }
+ if (MO.hasAllocatedReg())
+ OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ break;
+ case MachineOperand::MO_CCRegister:
+ OS << "%ccreg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg()) {
+ OS << "==";
+ OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ }
+ break;
+ case MachineOperand::MO_MachineRegister:
+ OutputReg(OS, MO.getMachineRegNum(), MRI);
+ break;
+ case MachineOperand::MO_SignExtendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_UnextendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_PCRelativeDisp: {
+ const Value* opVal = MO.getVRegValue();
+ bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
+ OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
+ if (opVal->hasName())
+ OS << opVal->getName();
+ else
+ OS << (const void*) opVal;
+ OS << ")";
+ break;
+ }
+ case MachineOperand::MO_MachineBasicBlock:
+ OS << "bb<"
+ << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
+ << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
+ break;
+ case MachineOperand::MO_FrameIndex:
+ OS << "<fi#" << MO.getFrameIndex() << ">";
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ OS << "<cp#" << MO.getConstantPoolIndex() << ">";
+ break;
+ case MachineOperand::MO_GlobalAddress:
+ OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
+ break;
+ case MachineOperand::MO_ExternalSymbol:
+ OS << "<es:" << MO.getSymbolName() << ">";
+ break;
+ default:
+ assert(0 && "Unrecognized operand type");
+ }
-void
-Set2OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& targetMachine,
- bool canDiscardResult,
- int op1Position,
- int resultPosition)
-{
- Set3OperandsFromInstr(minstr, vmInstrNode, targetMachine,
- canDiscardResult, op1Position,
- /*op2Position*/ -1, resultPosition);
+ if (CloseParen)
+ OS << ")";
}
+void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
+ unsigned StartOp = 0;
-unsigned
-Set3OperandsFromInstrJUNK(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& targetMachine,
- bool canDiscardResult,
- int op1Position,
- int op2Position,
- int resultPosition)
-{
- assert(op1Position >= 0);
- assert(resultPosition >= 0);
-
- unsigned returnFlags = 0x0;
-
- // Check if operand 1 is 0 and if so, try to use the register that gives 0, if any.
- Value* op1Value = vmInstrNode->leftChild()->getValue();
- bool isValidConstant;
- int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
- if (isValidConstant && intValue == 0 && targetMachine.zeroRegNum >= 0)
- minstr->SetMachineOperand(op1Position, /*regNum*/ targetMachine.zeroRegNum);
- else
- {
- if (op1Value->getValueType() == Value::ConstantVal)
- {// value is constant and must be loaded from constant pool
- returnFlags = returnFlags | (1 << op1Position);
- }
- minstr->SetMachineOperand(op1Position, MachineOperand::MO_Register,
- op1Value);
- }
+ // Specialize printing if op#0 is definition
+ if (getNumOperands() &&
+ (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
+ ::print(getOperand(0), OS, TM);
+ OS << " = ";
+ ++StartOp; // Don't print this operand again!
+ }
+ OS << TM.getInstrInfo().getName(getOpcode());
- // Check if operand 2 (if any) fits in the immediate field of the instruction,
- // of if it is 0 and can use a dedicated machine register
- if (op2Position >= 0)
- {
- Value* op2Value = vmInstrNode->rightChild()->getValue();
- int64_t immedValue;
- MachineOperand::VirtualRegisterType vregType;
- unsigned int machineRegNum;
-
- MachineOperand::MachineOperandType
- op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(),targetMachine,
- /*canUseImmed*/ true,
- vregType, machineRegNum, immedValue);
-
- if (op2type == MachineOperand::MO_Register)
- {
- if (vregType == MachineOperand::MO_MachineReg)
- minstr->SetMachineOperand(op2Position, machineRegNum);
- else
- {
- if (op2Value->getValueType() == Value::ConstantVal)
- {// value is constant and must be loaded from constant pool
- returnFlags = returnFlags | (1 << op2Position);
- }
- minstr->SetMachineOperand(op2Position, op2type, op2Value);
- }
- }
- else
- minstr->SetMachineOperand(op2Position, op2type, immedValue);
+ for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
+ const MachineOperand& mop = getOperand(i);
+ if (i != StartOp)
+ OS << ",";
+ OS << " ";
+ ::print(mop, OS, TM);
+
+ if (mop.opIsDefAndUse())
+ OS << "<def&use>";
+ else if (mop.opIsDefOnly())
+ OS << "<def>";
+ }
+
+ // code for printing implict references
+ if (getNumImplicitRefs()) {
+ OS << "\tImplicitRefs: ";
+ for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
+ OS << "\t";
+ OutputValue(OS, getImplicitRef(i));
+ if (getImplicitOp(i).opIsDefAndUse())
+ OS << "<def&use>";
+ else if (getImplicitOp(i).opIsDefOnly())
+ OS << "<def>";
}
+ }
- // If operand 3 (result) can be discarded, use a dead register if one exists
- if (canDiscardResult && targetMachine.zeroRegNum >= 0)
- minstr->SetMachineOperand(resultPosition, targetMachine.zeroRegNum);
- else
- minstr->SetMachineOperand(resultPosition, MachineOperand::MO_Register,
- vmInstrNode->getValue());
-
- return returnFlags;
+ OS << "\n";
}
-void
-Set3OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& targetMachine,
- bool canDiscardResult,
- int op1Position,
- int op2Position,
- int resultPosition)
+std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
{
- assert(op1Position >= 0);
- assert(resultPosition >= 0);
+ os << TargetInstrDescriptors[MI.opCode].Name;
- // operand 1
- minstr->SetMachineOperand(op1Position, MachineOperand::MO_Register,
- vmInstrNode->leftChild()->getValue());
+ for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
+ os << "\t" << MI.getOperand(i);
+ if (MI.getOperand(i).opIsDefOnly())
+ os << "<d>";
+ if (MI.getOperand(i).opIsDefAndUse())
+ os << "<d&u>";
+ }
- // operand 2 (if any)
- if (op2Position >= 0)
- minstr->SetMachineOperand(op2Position, MachineOperand::MO_Register,
- vmInstrNode->rightChild()->getValue());
+ // code for printing implict references
+ unsigned NumOfImpRefs = MI.getNumImplicitRefs();
+ if (NumOfImpRefs > 0) {
+ os << "\tImplicit: ";
+ for (unsigned z=0; z < NumOfImpRefs; z++) {
+ OutputValue(os, MI.getImplicitRef(z));
+ if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
+ if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
+ os << "\t";
+ }
+ }
- // result operand: if it can be discarded, use a dead register if one exists
- if (canDiscardResult && targetMachine.zeroRegNum >= 0)
- minstr->SetMachineOperand(resultPosition, targetMachine.zeroRegNum);
- else
- minstr->SetMachineOperand(resultPosition, MachineOperand::MO_Register,
- vmInstrNode->getValue());
+ return os << "\n";
}
-
-MachineOperand::MachineOperandType
-ChooseRegOrImmed(Value* val,
- MachineOpCode opCode,
- const TargetMachine& targetMachine,
- bool canUseImmed,
- MachineOperand::VirtualRegisterType& getVRegType,
- unsigned int& getMachineRegNum,
- int64_t& getImmedValue)
+std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
{
- MachineOperand::MachineOperandType opType = MachineOperand::MO_Register;
- getVRegType = MachineOperand::MO_VirtualReg;
- getMachineRegNum = 0;
- getImmedValue = 0;
+ if (MO.opHiBits32())
+ OS << "%lm(";
+ else if (MO.opLoBits32())
+ OS << "%lo(";
+ else if (MO.opHiBits64())
+ OS << "%hh(";
+ else if (MO.opLoBits64())
+ OS << "%hm(";
- // Check for the common case first: argument is not constant
- //
- if (val->getValueType() != Value::ConstantVal)
- return opType;
-
- // Now get the constant value and check if it fits in the IMMED field.
- // Take advantage of the fact that the max unsigned value will rarely
- // fit into any IMMED field and ignore that case (i.e., cast smaller
- // unsigned constants to signed).
- //
- bool isValidConstant;
- int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant);
-
- if (isValidConstant)
+ switch (MO.getType())
{
- if (intValue == 0 && targetMachine.zeroRegNum >= 0)
- {
- getVRegType = MachineOperand::MO_MachineReg;
- getMachineRegNum = targetMachine.zeroRegNum;
- }
- else if (canUseImmed &&
- targetMachine.machineInstrInfo[opCode].constantFitsInImmedField(intValue))
- {
- opType = MachineOperand::MO_SignExtendedImmed;
- getImmedValue = intValue;
- }
+ case MachineOperand::MO_VirtualRegister:
+ if (MO.hasAllocatedReg())
+ OutputReg(OS, MO.getAllocatedRegNum());
+
+ if (MO.getVRegValue()) {
+ if (MO.hasAllocatedReg()) OS << "==";
+ OS << "%vreg";
+ OutputValue(OS, MO.getVRegValue());
+ }
+ break;
+ case MachineOperand::MO_CCRegister:
+ OS << "%ccreg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg()) {
+ OS << "==";
+ OutputReg(OS, MO.getAllocatedRegNum());
+ }
+ break;
+ case MachineOperand::MO_MachineRegister:
+ OutputReg(OS, MO.getMachineRegNum());
+ break;
+ case MachineOperand::MO_SignExtendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_UnextendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_PCRelativeDisp:
+ {
+ const Value* opVal = MO.getVRegValue();
+ bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
+ OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
+ if (opVal->hasName())
+ OS << opVal->getName();
+ else
+ OS << (const void*) opVal;
+ OS << ")";
+ break;
+ }
+ case MachineOperand::MO_MachineBasicBlock:
+ OS << "bb<"
+ << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
+ << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
+ break;
+ case MachineOperand::MO_FrameIndex:
+ OS << "<fi#" << MO.getFrameIndex() << ">";
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ OS << "<cp#" << MO.getConstantPoolIndex() << ">";
+ break;
+ case MachineOperand::MO_GlobalAddress:
+ OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
+ break;
+ case MachineOperand::MO_ExternalSymbol:
+ OS << "<es:" << MO.getSymbolName() << ">";
+ break;
+ default:
+ assert(0 && "Unrecognized operand type");
+ break;
}
- return opType;
+ if (MO.flags &
+ (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
+ MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
+ OS << ")";
+
+ return OS;
}
projects / oota-llvm.git / blobdiff