Avoid unnecessarily casting away const.

[oota-llvm.git] / lib / CodeGen / LowerSubregs.cpp

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 1b7f70e05ab31fa564211ce6b16e580516eec679..4172b12857b7c985a8cf5e173c2db26b29fb1160 100644 (file)
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Christopher Lamb and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
@@ -12,7 +12,7 @@
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -63,6 +63,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    MachineBasicBlock *MBB = MI->getParent();
    MachineFunction &MF = *MBB->getParent();
    const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    
    assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
           MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
@@ -83,12 +84,12 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
      if (MRegisterInfo::isPhysicalRegister(DstReg)) {
        TRC = getPhysicalRegisterRegClass(MRI, DstReg);
      } else {
-       TRC = MF.getSSARegMap()->getRegClass(DstReg);
+       TRC = MF.getRegInfo().getRegClass(DstReg);
      }
      assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
              "Extract subreg and Dst must be of same register class");
 
-     MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
+     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
      MachineBasicBlock::iterator dMI = MI;
      DOUT << "subreg: " << *(--dMI);
    }
@@ -103,6 +104,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
   MachineFunction &MF = *MBB->getParent();
   const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 
+  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   unsigned DstReg = 0;
   unsigned SrcReg = 0;
   unsigned InsReg = 0;
@@ -155,9 +157,9 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
       if (MRegisterInfo::isPhysicalRegister(InsReg)) {
         TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
       } else {
-        TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+        TRC1 = MF.getRegInfo().getRegClass(InsReg);
       }
-      MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+      TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
       MachineBasicBlock::iterator dMI = MI;
@@ -179,12 +181,12 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     if (MRegisterInfo::isPhysicalRegister(DstReg)) {
       TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
     } else {
-      TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
+      TRC0 = MF.getRegInfo().getRegClass(DstReg);
     }
     assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
             "Insert superreg and Dst must be of same register class");
 
-    MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+    TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
@@ -204,9 +206,9 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     if (MRegisterInfo::isPhysicalRegister(InsReg)) {
       TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
     } else {
-      TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+      TRC1 = MF.getRegInfo().getRegClass(InsReg);
     }
-    MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+    TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;