Add explicit keywords.

[oota-llvm.git] / lib / CodeGen / LowerSubregs.cpp

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index ba2a193ca40a18acc4d40ea3d959683b060d159f..232dc061e5851dcd334a6892711f334723d5eaae 100644 (file)
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Christopher Lamb and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
@@ -12,8 +12,8 @@
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Debug.h"
@@ -46,13 +46,13 @@ FunctionPass *llvm::createLowerSubregsPass() {
 
 // Returns the Register Class of a physical register.
 static const TargetRegisterClass *getPhysicalRegisterRegClass(
-        const MRegisterInfo &MRI,
+        const TargetRegisterInfo &TRI,
         unsigned reg) {
-  assert(MRegisterInfo::isPhysicalRegister(reg) &&
+  assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
          "reg must be a physical register");
   // Pick the register class of the right type that contains this physreg.
-  for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
-         E = MRI.regclass_end(); I != E; ++I)
+  for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
+         E = TRI.regclass_end(); I != E; ++I)
     if ((*I)->contains(reg))
       return *I;
   assert(false && "Couldn't find the register class");
@@ -62,7 +62,8 @@ static const TargetRegisterClass *getPhysicalRegisterRegClass(
 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    MachineBasicBlock *MBB = MI->getParent();
    MachineFunction &MF = *MBB->getParent();
-   const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
+   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    
    assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
           MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
@@ -71,24 +72,24 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    unsigned SuperReg = MI->getOperand(1).getReg();
    unsigned SubIdx = MI->getOperand(2).getImm();
 
-   assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
+   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
           "Extract supperg source must be a physical register");
-   unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
+   unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
    unsigned DstReg = MI->getOperand(0).getReg();
 
    DOUT << "subreg: CONVERTING: " << *MI;
 
    if (SrcReg != DstReg) {
      const TargetRegisterClass *TRC = 0;
-     if (MRegisterInfo::isPhysicalRegister(DstReg)) {
-       TRC = getPhysicalRegisterRegClass(MRI, DstReg);
+     if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+       TRC = getPhysicalRegisterRegClass(TRI, DstReg);
      } else {
-       TRC = MF.getSSARegMap()->getRegClass(DstReg);
+       TRC = MF.getRegInfo().getRegClass(DstReg);
      }
-     assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+     assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
              "Extract subreg and Dst must be of same register class");
 
-     MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
+     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
      MachineBasicBlock::iterator dMI = MI;
      DOUT << "subreg: " << *(--dMI);
    }
@@ -102,7 +103,8 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
   MachineFunction &MF = *MBB->getParent();
-  const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 
+  const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); 
+  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   unsigned DstReg = 0;
   unsigned SrcReg = 0;
   unsigned InsReg = 0;
@@ -131,13 +133,13 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     assert(0 && "Malformed extract_subreg");
 
   assert(SubIdx != 0 && "Invalid index for extract_subreg");
-  unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
+  unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 
-  assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
+  assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
          "Insert superreg source must be in a physical register");
-  assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
+  assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
          "Insert destination must be in a physical register");
-  assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
+  assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
          "Inserted value must be in a physical register");
 
   DOUT << "subreg: CONVERTING: " << *MI;
@@ -146,18 +148,18 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   // of the destination, we copy the subreg into the source
   // However, this is only safe if the insert instruction is the kill
   // of the source register
-  bool revCopyOrder = MRI.isSubRegOf(InsReg, DstReg);    
+  bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
   if (revCopyOrder && InsReg != DstSubReg) {
     if (MI->getOperand(1).isKill()) {
-      DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
+      DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
       // Insert sub-register copy
       const TargetRegisterClass *TRC1 = 0;
-      if (MRegisterInfo::isPhysicalRegister(InsReg)) {
-        TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+      if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+        TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
       } else {
-        TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+        TRC1 = MF.getRegInfo().getRegClass(InsReg);
       }
-      MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+      TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
       MachineBasicBlock::iterator dMI = MI;
@@ -176,15 +178,15 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   if (SrcReg != DstReg) {
     // Insert super-register copy
     const TargetRegisterClass *TRC0 = 0;
-    if (MRegisterInfo::isPhysicalRegister(DstReg)) {
-      TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
+    if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+      TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
     } else {
-      TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
+      TRC0 = MF.getRegInfo().getRegClass(DstReg);
     }
-    assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+    assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
             "Insert superreg and Dst must be of same register class");
 
-    MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+    TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
@@ -201,12 +203,12 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   if (!revCopyOrder && InsReg != DstSubReg) {
     // Insert sub-register copy
     const TargetRegisterClass *TRC1 = 0;
-    if (MRegisterInfo::isPhysicalRegister(InsReg)) {
-      TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+    if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+      TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
     } else {
-      TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+      TRC1 = MF.getRegInfo().getRegClass(InsReg);
     }
-    MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+    TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;