//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Christopher Lamb and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
// Returns the Register Class of a physical register.
static const TargetRegisterClass *getPhysicalRegisterRegClass(
- const MRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI,
unsigned reg) {
- assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
"reg must be a physical register");
// Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
- E = MRI.regclass_end(); I != E; ++I)
+ for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
+ E = TRI.regclass_end(); I != E; ++I)
if ((*I)->contains(reg))
return *I;
assert(false && "Couldn't find the register class");
return 0;
}
-static bool isSubRegOf(const MRegisterInfo &MRI,
- unsigned SubReg,
- unsigned SupReg) {
- const TargetRegisterDesc &RD = MRI[SubReg];
- for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
- if (*reg == SupReg)
- return true;
-
- return false;
-}
-
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
- MI->getOperand(2).isImm() && "Malformed extract_subreg");
+ MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
unsigned SuperReg = MI->getOperand(1).getReg();
unsigned SubIdx = MI->getOperand(2).getImm();
- assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
"Extract supperg source must be a physical register");
- unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
+ unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
unsigned DstReg = MI->getOperand(0).getReg();
DOUT << "subreg: CONVERTING: " << *MI;
if (SrcReg != DstReg) {
const TargetRegisterClass *TRC = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC = getPhysicalRegisterRegClass(MRI, DstReg);
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ TRC = getPhysicalRegisterRegClass(TRI, DstReg);
} else {
- TRC = MF.getSSARegMap()->getRegClass(DstReg);
+ TRC = MF.getRegInfo().getRegClass(DstReg);
}
- assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+ assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
"Extract subreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC);
+ TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
}
DOUT << "\n";
- MBB->erase(MI);
+ MBB->remove(MI);
return true;
}
bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
- const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
unsigned DstReg = 0;
unsigned SrcReg = 0;
unsigned InsReg = 0;
if (MI->getNumOperands() == 3) {
assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
- MI->getOperand(2).isImm() && "Invalid extract_subreg");
+ MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
DstReg = MI->getOperand(0).getReg();
SrcReg = DstReg;
InsReg = MI->getOperand(1).getReg();
assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
(MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
- MI->getOperand(3).isImm() && "Invalid extract_subreg");
+ MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
DstReg = MI->getOperand(0).getReg();
SrcReg = MI->getOperand(1).getReg();
InsReg = MI->getOperand(2).getReg();
assert(0 && "Malformed extract_subreg");
assert(SubIdx != 0 && "Invalid index for extract_subreg");
- unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
+ unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register");
DOUT << "subreg: CONVERTING: " << *MI;
// of the destination, we copy the subreg into the source
// However, this is only safe if the insert instruction is the kill
// of the source register
- bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
- if (revCopyOrder) {
+ bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
+ if (revCopyOrder && InsReg != DstSubReg) {
if (MI->getOperand(1).isKill()) {
- DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
+ DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
// Insert sub-register copy
const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+ if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+ TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
} else {
- TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+ TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
-
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+
+#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
+#endif
} else {
assert(0 && "Don't know how to convert this insert");
}
}
+#ifndef NDEBUG
+ if (InsReg == DstSubReg) {
+ DOUT << "subreg: Eliminated subreg copy\n";
+ }
+#endif
if (SrcReg != DstReg) {
// Insert super-register copy
const TargetRegisterClass *TRC0 = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
} else {
- TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
+ TRC0 = MF.getRegInfo().getRegClass(DstReg);
}
- assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
+ assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
"Insert superreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
+ TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+
+#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
+#endif
+ }
+
+#ifndef NDEBUG
+ if (SrcReg == DstReg) {
+ DOUT << "subreg: Eliminated superreg copy\n";
}
+#endif
if (!revCopyOrder && InsReg != DstSubReg) {
// Insert sub-register copy
const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
+ if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
+ TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
} else {
- TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+ TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
-
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+
+#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
+#endif
}
DOUT << "\n";
- MBB->erase(MI);
+ MBB->remove(MI);
return true;
}
projects / oota-llvm.git / blobdiff