//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
void LiveVariables::VarInfo::dump() const {
- cerr << "Register Defined by: ";
- if (DefInst)
- cerr << *DefInst;
- else
- cerr << "<null>\n";
cerr << " Alive in blocks: ";
for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
if (AliveBlocks[i]) cerr << i << ", ";
+ cerr << " Used in blocks: ";
+ for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
+ if (UsedBlocks[i]) cerr << i << ", ";
cerr << "\n Killed by:";
if (Kills.empty())
cerr << " No instructions.\n";
}
VarInfo &VI = VirtRegInfo[RegIdx];
VI.AliveBlocks.resize(MF->getNumBlockIDs());
+ VI.UsedBlocks.resize(MF->getNumBlockIDs());
return VI;
}
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
+ if (MO.isRegister() && MO.isKill()) {
if ((MO.getReg() == Reg) ||
(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
MRegisterInfo::isPhysicalRegister(Reg) &&
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
+ if (MO.isRegister() && MO.isDead()) {
if ((MO.getReg() == Reg) ||
(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
MRegisterInfo::isPhysicalRegister(Reg) &&
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return true;
}
return false;
}
-void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
+ MachineBasicBlock *DefBlock,
MachineBasicBlock *MBB,
std::vector<MachineBasicBlock*> &WorkList) {
unsigned BBNum = MBB->getNumber();
-
+
// Check to see if this basic block is one of the killing blocks. If so,
// remove it...
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
break;
}
-
- if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
+
+ if (MBB == DefBlock) return; // Terminate recursion
if (VRInfo.AliveBlocks[BBNum])
return; // We already know the block is live
WorkList.push_back(*PI);
}
-void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
+ MachineBasicBlock *DefBlock,
MachineBasicBlock *MBB) {
std::vector<MachineBasicBlock*> WorkList;
- MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
+ MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
while (!WorkList.empty()) {
MachineBasicBlock *Pred = WorkList.back();
WorkList.pop_back();
- MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
+ MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
}
}
-void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
+void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
MachineInstr *MI) {
- assert(VRInfo.DefInst && "Register use before def!");
+ MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
+ assert(MRI.getVRegDef(reg) && "Register use before def!");
+ unsigned BBNum = MBB->getNumber();
+
+ VarInfo& VRInfo = getVarInfo(reg);
+ VRInfo.UsedBlocks[BBNum] = true;
VRInfo.NumUses++;
// Check to see if this basic block is already a kill block...
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefInst->getParent() &&
+ assert(MBB != MRI.getVRegDef(reg)->getParent() &&
"Should have kill for defblock!");
// Add a new kill entry for this basic block.
// If this virtual register is already marked as alive in this basic block,
// that means it is alive in at least one of the successor block, it's not
// a kill.
- if (!VRInfo.AliveBlocks[MBB->getNumber()])
+ if (!VRInfo.AliveBlocks[BBNum])
VRInfo.Kills.push_back(MI);
// Update all dominating blocks to mark them known live.
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
E = MBB->pred_end(); PI != E; ++PI)
- MarkVirtRegAliveInBlock(VRInfo, *PI);
-}
-
-bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
- bool AddIfNotFound) {
- bool Found = false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
- MO.setIsKill();
- Found = true;
- break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isKill())
- // A super-register kill already exists.
- return true;
- }
- }
-
- // If not found, this means an alias of one of the operand is killed. Add a
- // new implicit operand if required.
- if (!Found && AddIfNotFound) {
- MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- return true;
- }
- return Found;
-}
-
-bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
- bool AddIfNotFound) {
- bool Found = false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
- MO.setIsDead();
- Found = true;
- break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isDead())
- // There exists a super-register that's marked dead.
- return true;
- }
- }
-
- // If not found, this means an alias of one of the operand is dead. Add a
- // new implicit operand.
- if (!Found && AddIfNotFound) {
- MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
- true/*IsDead*/);
- return true;
- }
- return Found;
+ MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
}
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
- // There is a now a proper use, forget about the last partial use.
- PhysRegPartUse[Reg] = NULL;
-
// Turn previous partial def's into read/mod/write.
for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
MachineInstr *Def = PhysRegPartDef[Reg][i];
// First one is just a def. This means the use is reading some undef bits.
if (i != 0)
- Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
+ true/*IsImp*/,true/*IsKill*/));
+ Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
}
PhysRegPartDef[Reg].clear();
// A: EAX = ...
// B: = AX
// Add implicit def to A.
- if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
+ if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
+ !PhysRegUsed[Reg]) {
MachineInstr *Def = PhysRegInfo[Reg];
if (!Def->findRegisterDefOperand(Reg))
- Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
+ true/*IsImp*/));
}
+ // There is a now a proper use, forget about the last partial use.
+ PhysRegPartUse[Reg] = NULL;
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
MachineInstr *LastRef = PhysRegInfo[SubReg];
- if (LastRef != RefMI)
- SubKills.insert(SubReg);
- else if (!HandlePhysRegKill(SubReg, RefMI, SubKills))
+ if (LastRef != RefMI ||
+ !HandlePhysRegKill(SubReg, RefMI, SubKills))
SubKills.insert(SubReg);
}
void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
SmallSet<unsigned, 4> &SubKills) {
if (SubKills.count(Reg) == 0)
- addRegisterKilled(Reg, MI, true);
+ MI->addRegisterKilled(Reg, RegInfo, true);
else {
for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
SmallSet<unsigned, 4> SubKills;
if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
- addRegisterKilled(Reg, RefMI);
+ RefMI->addRegisterKilled(Reg, RegInfo, true);
return true;
} else {
// Some sub-registers are killed by another MI.
if (PhysRegUsed[Reg]) {
if (!HandlePhysRegKill(Reg, LastRef)) {
if (PhysRegPartUse[Reg])
- addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
+ PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
}
} else if (PhysRegPartUse[Reg])
// Add implicit use / kill to last partial use.
- addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
- else
- addRegisterDead(Reg, LastRef);
+ PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
+ else if (LastRef != MI)
+ // Defined, but not used. However, watch out for cases where a super-reg
+ // is also defined on the same MI.
+ LastRef->addRegisterDead(Reg, RegInfo);
}
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
if (PhysRegUsed[SubReg]) {
if (!HandlePhysRegKill(SubReg, LastRef)) {
if (PhysRegPartUse[SubReg])
- addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
+ PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
}
} else if (PhysRegPartUse[SubReg])
// Add implicit use / kill to last use of a sub-register.
- addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
- else
- addRegisterDead(SubReg, LastRef);
+ PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
+ else if (LastRef != MI)
+ // This must be a def of the subreg on the same MI.
+ LastRef->addRegisterDead(SubReg, RegInfo);
}
}
if (MI) {
for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
unsigned SuperReg = *SuperRegs; ++SuperRegs) {
- if (PhysRegInfo[SuperReg]) {
+ if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
// The larger register is previously defined. Now a smaller part is
// being re-defined. Treat it as read/mod/write.
// EAX =
// AX = EAX<imp-use,kill>, EAX<imp-def>
- MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
+ MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
+ true/*IsImp*/,true/*IsKill*/));
+ MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
+ true/*IsImp*/));
PhysRegInfo[SuperReg] = MI;
PhysRegUsed[SuperReg] = false;
PhysRegPartUse[SuperReg] = NULL;
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
RegInfo = MF->getTarget().getRegisterInfo();
+ MachineRegisterInfo& MRI = mf.getRegInfo();
assert(RegInfo && "Target doesn't have register information?");
ReservedRegisters = RegInfo->getReservedRegs(mf);
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
- HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
+ HandleVirtRegUse(MO.getReg(), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
!ReservedRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
-
- assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
- VRInfo.DefInst = MI;
// Defaults to dead
VRInfo.Kills.push_back(MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
E = VarInfoVec.end(); I != E; ++I) {
- VarInfo& VRInfo = getVarInfo(*I);
- assert(VRInfo.DefInst && "Register use before def (or no def)!");
-
// Only mark it alive only in the block we are representing.
- MarkVirtRegAliveInBlock(VRInfo, MBB);
+ MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
+ MBB);
}
}
// Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
- if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
+ if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
MachineInstr *Ret = &MBB->back();
- for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
- E = MF->liveout_end(); I != E; ++I) {
+ for (MachineRegisterInfo::liveout_iterator
+ I = MF->getRegInfo().liveout_begin(),
+ E = MF->getRegInfo().liveout_end(); I != E; ++I) {
assert(MRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
// Add live-out registers as implicit uses.
if (Ret->findRegisterUseOperandIdx(*I) == -1)
- Ret->addRegOperand(*I, false, true);
+ Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
}
}
//
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
- if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
- addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
- VirtRegInfo[i].Kills[j]);
+ if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
+ MRegisterInfo::FirstVirtualRegister))
+ VirtRegInfo[i].Kills[j]->addRegisterDead(i +
+ MRegisterInfo::FirstVirtualRegister,
+ RegInfo);
else
- addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
- VirtRegInfo[i].Kills[j]);
+ VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
+ MRegisterInfo::FirstVirtualRegister,
+ RegInfo);
}
// Check to make sure there are no unreachable blocks in the MC CFG for the
VarInfo &VI = getVarInfo(Reg);
if (MO.isDef()) {
if (MO.isDead()) {
- MO.unsetIsDead();
+ MO.setIsDead(false);
addVirtualRegisterDead(Reg, NewMI);
}
- // Update the defining instruction.
- if (VI.DefInst == OldMI)
- VI.DefInst = NewMI;
}
if (MO.isKill()) {
- MO.unsetIsKill();
+ MO.setIsKill(false);
addVirtualRegisterKilled(Reg, NewMI);
}
// If this is a kill of the value, update the VI kills list.
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
- MO.unsetIsKill();
+ if (MO.isRegister() && MO.isKill()) {
+ MO.setIsKill(false);
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
- MO.unsetIsDead();
+ if (MO.isRegister() && MO.isDead()) {
+ MO.setIsDead(false);
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
+ PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()].
push_back(BBI->getOperand(i).getReg());
}
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