WorkList.push_back(*PI);
}
-void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
MachineBasicBlock *DefBlock,
MachineBasicBlock *MBB) {
std::vector<MachineBasicBlock*> WorkList;
MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
+
while (!WorkList.empty()) {
MachineBasicBlock *Pred = WorkList.back();
WorkList.pop_back();
}
}
-
void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
MachineInstr *MI) {
- MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
+ const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
assert(MRI.getVRegDef(reg) && "Register use before def!");
unsigned BBNum = MBB->getNumber();
if (!VRInfo.AliveBlocks[BBNum])
VRInfo.Kills.push_back(MI);
- // Update all dominating blocks to mark them known live.
+ // Update all dominating blocks to mark them as "known live".
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
E = MBB->pred_end(); PI != E; ++PI)
MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
}
+/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
+/// implicit defs to a machine instruction if there was an earlier def of its
+/// super-register.
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
// Turn previous partial def's into read/mod/write.
for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
MachineInstr *Def = PhysRegPartDef[Reg][i];
+
// First one is just a def. This means the use is reading some undef bits.
if (i != 0)
- Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
- true/*IsImp*/,true/*IsKill*/));
- Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
+ Def->addOperand(MachineOperand::CreateReg(Reg,
+ false /*IsDef*/,
+ true /*IsImp*/,
+ true /*IsKill*/));
+
+ Def->addOperand(MachineOperand::CreateReg(Reg,
+ true /*IsDef*/,
+ true /*IsImp*/));
}
PhysRegPartDef[Reg].clear();
// There was an earlier def of a super-register. Add implicit def to that MI.
- // A: EAX = ...
- // B: = AX
+ //
+ // A: EAX = ...
+ // B: ... = AX
+ //
// Add implicit def to A.
if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
!PhysRegUsed[Reg]) {
MachineInstr *Def = PhysRegInfo[Reg];
+
if (!Def->findRegisterDefOperand(Reg))
- Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
- true/*IsImp*/));
+ Def->addOperand(MachineOperand::CreateReg(Reg,
+ true /*IsDef*/,
+ true /*IsImp*/));
}
// There is a now a proper use, forget about the last partial use.
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
+ // Now reset the use information for the sub-registers.
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
+ PhysRegPartUse[SubReg] = NULL;
PhysRegInfo[SubReg] = MI;
PhysRegUsed[SubReg] = true;
}
for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
unsigned SuperReg = *SuperRegs; ++SuperRegs) {
- // Remember the partial use of this superreg if it was previously defined.
+ // Remember the partial use of this super-register if it was previously
+ // defined.
bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
- if (!HasPrevDef) {
+
+ if (!HasPrevDef)
+ // No need to go up more levels. A def of a register also sets its sub-
+ // registers. So if PhysRegInfo[SuperReg] is NULL, it means SuperReg's
+ // super-registers are not previously defined.
for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
- unsigned SSReg = *SSRegs; ++SSRegs) {
+ unsigned SSReg = *SSRegs; ++SSRegs)
if (PhysRegInfo[SSReg] != NULL) {
HasPrevDef = true;
break;
}
- }
- }
+
if (HasPrevDef) {
PhysRegInfo[SuperReg] = MI;
PhysRegPartUse[SuperReg] = MI;
}
}
-bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
- SmallSet<unsigned, 4> &SubKills) {
+/// addRegisterKills - For all of a register's sub-registers that are killed in
+/// at this machine instruction, mark them as "killed". (If the machine operand
+/// isn't found, add it first.)
+void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
+ SmallSet<unsigned, 4> &SubKills) {
+ if (SubKills.count(Reg) == 0) {
+ MI->addRegisterKilled(Reg, RegInfo, true);
+ return;
+ }
+
for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs) {
- MachineInstr *LastRef = PhysRegInfo[SubReg];
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, MI, SubKills);
+}
+
+/// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
+/// if:
+///
+/// - The register has no sub-registers and the machine instruction is the
+/// last def/use of the register, or
+/// - The register has sub-registers and none of them are killed elsewhere.
+///
+/// SubKills is filled with the set of sub-registers that are killed elsewhere.
+bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
+ SmallSet<unsigned, 4> &SubKills) {
+ const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+
+ for (; unsigned SubReg = *SubRegs; ++SubRegs) {
+ const MachineInstr *LastRef = PhysRegInfo[SubReg];
+
if (LastRef != RefMI ||
!HandlePhysRegKill(SubReg, RefMI, SubKills))
SubKills.insert(SubReg);
}
- if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
+ if (*SubRegs == 0) {
// No sub-registers, just check if reg is killed by RefMI.
if (PhysRegInfo[Reg] == RefMI)
return true;
- } else if (SubKills.empty())
- // None of the sub-registers are killed elsewhere...
+ } else if (SubKills.empty()) {
+ // None of the sub-registers are killed elsewhere.
return true;
- return false;
-}
-
-void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
- SmallSet<unsigned, 4> &SubKills) {
- if (SubKills.count(Reg) == 0)
- MI->addRegisterKilled(Reg, RegInfo, true);
- else {
- for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- addRegisterKills(SubReg, MI, SubKills);
}
+
+ return false;
}
+/// HandlePhysRegKill - Returns true if the whole register is killed in the
+/// machine instruction. If only some of its sub-registers are killed in this
+/// machine instruction, then mark those as killed and return false.
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
SmallSet<unsigned, 4> SubKills;
+
if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
+ // This machine instruction kills this register.
RefMI->addRegisterKilled(Reg, RegInfo, true);
return true;
- } else {
- // Some sub-registers are killed by another MI.
- for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- addRegisterKills(SubReg, RefMI, SubKills);
- return false;
}
+
+ // Some sub-registers are killed by another machine instruction.
+ for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, RefMI, SubKills);
+
+ return false;
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
if (PhysRegPartUse[Reg])
PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
}
- } else if (PhysRegPartUse[Reg])
+ } else if (PhysRegPartUse[Reg]) {
// Add implicit use / kill to last partial use.
PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
- else if (LastRef != MI)
+ } else if (LastRef != MI) {
// Defined, but not used. However, watch out for cases where a super-reg
// is also defined on the same MI.
LastRef->addRegisterDead(Reg, RegInfo);
+ }
}
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
if (PhysRegPartUse[SubReg])
PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
}
- } else if (PhysRegPartUse[SubReg])
+ } else if (PhysRegPartUse[SubReg]) {
// Add implicit use / kill to last use of a sub-register.
PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
- else if (LastRef != MI)
+ } else if (LastRef != MI) {
// This must be a def of the subreg on the same MI.
LastRef->addRegisterDead(SubReg, RegInfo);
+ }
}
}
PhysRegUsed[Reg] = false;
PhysRegPartDef[Reg].clear();
PhysRegPartUse[Reg] = NULL;
+
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
PhysRegInfo[SubReg] = MI;
std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
- /// Get some space for a respectable number of registers...
+ /// Get some space for a respectable number of registers.
VirtRegInfo.resize(64);
analyzePHINodes(mf);
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
// nodes, which are treated as a special case).
- //
MachineBasicBlock *Entry = MF->begin();
SmallPtrSet<MachineBasicBlock*,16> Visited;
+
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
DFI != E; ++DFI) {
if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
- // Process all uses...
+ // Process all uses.
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
const MachineOperand &MO = MI->getOperand(i);
+
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
unsigned MOReg = MO.getReg();
+
if (TargetRegisterInfo::isVirtualRegister(MOReg))
HandleVirtRegUse(MOReg, MBB, MI);
else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
}
}
- // Process all defs...
+ // Process all defs.
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
const MachineOperand &MO = MI->getOperand(i);
+
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
unsigned MOReg = MO.getReg();
+
if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
VarInfo &VRInfo = getVarInfo(MOReg);
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
- E = VarInfoVec.end(); I != E; ++I) {
- // Only mark it alive only in the block we are representing.
+ E = VarInfoVec.end(); I != E; ++I)
+ // Mark it alive only in the block we are representing.
MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
MBB);
- }
}
- // Finally, if the last instruction in the block is a return, make sure to mark
- // it as using all of the live-out values in the function.
+ // Finally, if the last instruction in the block is a return, make sure to
+ // mark it as using all of the live-out values in the function.
if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
MachineInstr *Ret = &MBB->back();
+
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
+
// Add live-out registers as implicit uses.
if (Ret->findRegisterUseOperandIdx(*I) == -1)
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
}
// Loop over PhysRegInfo, killing any registers that are available at the
- // end of the basic block. This also resets the PhysRegInfo map.
+ // end of the basic block. This also resets the PhysRegInfo map.
for (unsigned i = 0; i != NumRegs; ++i)
if (PhysRegInfo[i])
HandlePhysRegDef(i, 0);
// Clear some states between BB's. These are purely local information.
for (unsigned i = 0; i != NumRegs; ++i)
PhysRegPartDef[i].clear();
+
std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
// Convert and transfer the dead / killed information we have gathered into
// VirtRegInfo onto MI's.
- //
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
- for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
- if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
- TargetRegisterInfo::FirstVirtualRegister))
- VirtRegInfo[i].Kills[j]->addRegisterDead(i +
- TargetRegisterInfo::FirstVirtualRegister,
- RegInfo);
+ for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
+ if (VirtRegInfo[i].Kills[j] ==
+ MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
+ VirtRegInfo[i]
+ .Kills[j]->addRegisterDead(i +
+ TargetRegisterInfo::FirstVirtualRegister,
+ RegInfo);
else
- VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
- TargetRegisterInfo::FirstVirtualRegister,
- RegInfo);
- }
+ VirtRegInfo[i]
+ .Kills[j]->addRegisterKilled(i +
+ TargetRegisterInfo::FirstVirtualRegister,
+ RegInfo);
// Check to make sure there are no unreachable blocks in the MC CFG for the
// function. If so, it is due to a bug in the instruction selector or some
return false;
}
-/// instructionChanged - When the address of an instruction changes, this
-/// method should be called so that live variables can update its internal
-/// data structures. This removes the records for OldMI, transfering them to
-/// the records for NewMI.
+/// instructionChanged - When the address of an instruction changes, this method
+/// should be called so that live variables can update its internal data
+/// structures. This removes the records for OldMI, transfering them to the
+/// records for NewMI.
void LiveVariables::instructionChanged(MachineInstr *OldMI,
MachineInstr *NewMI) {
// If the instruction defines any virtual registers, update the VarInfo,
}
/// analyzePHINodes - Gather information about the PHI nodes in here. In
-/// particular, we want to map the variable information of a virtual
-/// register which is used in a PHI node. We map that to the BB the vreg is
-/// coming from.
+/// particular, we want to map the variable information of a virtual register
+/// which is used in a PHI node. We map that to the BB the vreg is coming from.
///
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
projects / oota-llvm.git / blobdiff