#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
static cl::opt<bool> EnableAggressiveRemat("aggressive-remat", cl::Hidden);
+static cl::opt<bool> EnableFastSpilling("fast-spill",
+ cl::init(false), cl::Hidden);
+
STATISTIC(numIntervals, "Number of original intervals");
-STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
STATISTIC(numFolds , "Number of loads/stores folded into instructions");
STATISTIC(numSplits , "Number of intervals split");
AU.addRequired<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
- AU.addPreservedID(PHIEliminationID);
- AU.addRequiredID(PHIEliminationID);
+
+ if (!StrongPHIElim) {
+ AU.addPreservedID(PHIEliminationID);
+ AU.addRequiredID(PHIEliminationID);
+ }
+
AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU);
}
void LiveIntervals::releaseMemory() {
+ // Free the live intervals themselves.
+ for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
+ E = r2iMap_.end(); I != E; ++I)
+ delete I->second;
+
MBB2IdxMap.clear();
Idx2MBBMap.clear();
mi2iMap_.clear();
I != E; ++I) {
bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
+ inserted = true;
i2miMap_.push_back(I);
MIIndex += InstrSlots::NUM;
FunctionSize++;
- // Insert an empty slot after every instruction.
- MIIndex += InstrSlots::NUM;
- i2miMap_.push_back(0);
+ // Insert max(1, numdefs) empty slots after every instruction.
+ unsigned Slots = I->getDesc().getNumDefs();
+ if (Slots == 0)
+ Slots = 1;
+ MIIndex += InstrSlots::NUM * Slots;
+ while (Slots--)
+ i2miMap_.push_back(0);
}
// Set the MBB2IdxMap entry for this MBB.
MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
}
-
std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
if (!OldI2MI.empty())
- for (iterator OI = begin(), OE = end(); OI != OE; ++OI)
- for (LiveInterval::iterator LI = OI->second.begin(),
- LE = OI->second.end(); LI != LE; ++LI) {
+ for (iterator OI = begin(), OE = end(); OI != OE; ++OI) {
+ for (LiveInterval::iterator LI = OI->second->begin(),
+ LE = OI->second->end(); LI != LE; ++LI) {
// Remap the start index of the live range to the corresponding new
// number, or our best guess at what it _should_ correspond to if the
// instruction or its predecessor.
unsigned index = LI->start / InstrSlots::NUM;
unsigned offset = LI->start % InstrSlots::NUM;
- if (offset == InstrSlots::LOAD || LI->valno->def == ~0U) {
+ if (offset == InstrSlots::LOAD) {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->start);
// Take the pair containing the index
std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
+ (I == OldI2MBB.end() && OldI2MBB.size()>0) ? (I-1): I;
LI->start = getMBBStartIdx(J->second);
} else {
// following instruction.
index = (LI->end - 1) / InstrSlots::NUM;
offset = LI->end % InstrSlots::NUM;
- if (LI->valno->hasPHIKill && !OldI2MI[index]) {
- // Special handling for when this was previously killed by a PHI, but
- // the PHI has now been removed. We need to trim the live interval
- // to die at the end of the preceding block.
+ if (offset == InstrSlots::LOAD) {
+ // VReg dies at end of block.
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
- // Take the pair containing the index
- std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
+ --I;
- MachineBasicBlock* StartMBB = J->second;
- MachineBasicBlock* CurrMBB = J->second;
-
- while (CurrMBB == StartMBB) {
- while (index > 0 && !OldI2MI[index]) --index;
- CurrMBB = OldI2MI[index]->getParent();
- if (!StartMBB) StartMBB = CurrMBB;
-
- --index;
- }
-
- LI->end = getMBBEndIdx(CurrMBB) + 1;
- } else if (offset == InstrSlots::USE) {
- std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
- // Take the pair containing the index
- std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
-
- LI->end = getMBBEndIdx(J->second) + 1;
+ LI->end = getMBBEndIdx(I->second) + 1;
} else {
unsigned idx = index;
while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
else
LI->end = InstrSlots::NUM * i2miMap_.size();
}
+ }
+
+ for (LiveInterval::vni_iterator VNI = OI->second->vni_begin(),
+ VNE = OI->second->vni_end(); VNI != VNE; ++VNI) {
+ VNInfo* vni = *VNI;
// Remap the VNInfo def index, which works the same as the
- // start indices above.
- VNInfo* vni = LI->valno;
- if (vni->def != ~0U) {
- index = vni->def / InstrSlots::NUM;
- offset = vni->def % InstrSlots::NUM;
+ // start indices above. VN's with special sentinel defs
+ // don't need to be remapped.
+ if (vni->def != ~0U && vni->def != ~1U) {
+ unsigned index = vni->def / InstrSlots::NUM;
+ unsigned offset = vni->def % InstrSlots::NUM;
if (offset == InstrSlots::LOAD) {
std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(),
- vni->def);
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->def);
// Take the pair containing the index
std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
+ (I == OldI2MBB.end() && OldI2MBB.size()>0) ? (I-1): I;
vni->def = getMBBStartIdx(J->second);
-
} else {
vni->def = mi2iMap_[OldI2MI[index]] + offset;
}
// Remap the VNInfo kill indices, which works the same as
// the end indices above.
for (size_t i = 0; i < vni->kills.size(); ++i) {
- index = (vni->kills[i]-1) / InstrSlots::NUM;
- offset = vni->kills[i] % InstrSlots::NUM;
+ // PHI kills don't need to be remapped.
+ if (!vni->kills[i]) continue;
- if (LI->valno->hasPHIKill && !OldI2MI[index]) {
- // Special handling for when this was previously killed by a PHI,
- // but the PHI has now been removed. We need to trim the live
- // interval to die at the end of the preceding block.
- std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
- // Take the pair containing the index
- std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
-
- MachineBasicBlock* StartMBB = J->second;
- MachineBasicBlock* CurrMBB = J->second;
-
- while (CurrMBB == StartMBB) {
- while (index > 0 && !OldI2MI[index]) --index;
- CurrMBB = OldI2MI[index]->getParent();
- if (!StartMBB) StartMBB = CurrMBB;
-
- --index;
- }
-
- vni->kills[i] = getMBBEndIdx(CurrMBB) + 1;
- } else if (offset == InstrSlots::USE) {
+ unsigned index = (vni->kills[i]-1) / InstrSlots::NUM;
+ unsigned offset = vni->kills[i] % InstrSlots::NUM;
+ if (offset == InstrSlots::LOAD) {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
- // Take the pair containing the index
- std::vector<IdxMBBPair>::const_iterator J =
- ((I != OldI2MBB.end() && I->first > index) ||
- (I == OldI2MBB.end() && OldI2MBB.size()>0)) ? (I-1): I;
+ --I;
- vni->kills[i] = getMBBEndIdx(J->second) + 1;
+ vni->kills[i] = getMBBEndIdx(I->second);
} else {
unsigned idx = index;
- while (!OldI2MI[index]) ++index;
while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
if (index != OldI2MI.size())
}
}
}
+ }
}
/// runOnMachineFunction - Register allocate the whole function
numIntervals += getNumIntervals();
- DOUT << "********** INTERVALS **********\n";
- for (iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(DOUT, tri_);
- DOUT << "\n";
- }
-
- numIntervalsAfter += getNumIntervals();
DEBUG(dump());
return true;
}
void LiveIntervals::print(std::ostream &O, const Module* ) const {
O << "********** INTERVALS **********\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(O, tri_);
+ I->second->print(O, tri_);
O << "\n";
}
if (index == end) break;
MachineInstr *MI = getInstructionFromIndex(index);
- unsigned SrcReg, DstReg;
- if (tii_->isMoveInstr(*MI, SrcReg, DstReg))
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
if (SrcReg == li.reg || DstReg == li.reg)
continue;
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
- if (!mop.isRegister())
+ if (!mop.isReg())
continue;
unsigned PhysReg = mop.getReg();
if (PhysReg == 0 || PhysReg == li.reg)
return false;
}
+/// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except
+/// it can check use as well.
+bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li,
+ unsigned Reg, bool CheckUse,
+ SmallPtrSet<MachineInstr*,32> &JoinedCopies) {
+ for (LiveInterval::Ranges::const_iterator
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ for (unsigned index = getBaseIndex(I->start),
+ end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
+ index += InstrSlots::NUM) {
+ // Skip deleted instructions.
+ MachineInstr *MI = 0;
+ while (index != end) {
+ MI = getInstructionFromIndex(index);
+ if (MI)
+ break;
+ index += InstrSlots::NUM;
+ }
+ if (index == end) break;
+
+ if (JoinedCopies.count(MI))
+ continue;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (!MO.isReg())
+ continue;
+ if (MO.isUse() && !CheckUse)
+ continue;
+ unsigned PhysReg = MO.getReg();
+ if (PhysReg == 0 || TargetRegisterInfo::isVirtualRegister(PhysReg))
+ continue;
+ if (tri_->isSubRegister(Reg, PhysReg))
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+
void LiveIntervals::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
cerr << tri_->getName(reg);
if (interval.empty()) {
// Get the Idx of the defining instructions.
unsigned defIndex = getDefIndex(MIIdx);
+ // Earlyclobbers move back one.
+ if (MO.isEarlyClobber())
+ defIndex = getUseIndex(MIIdx);
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg;
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
- tii_->isMoveInstr(*mi, SrcReg, DstReg))
+ tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = mi;
+ // Earlyclobbers move back one.
ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
assert(ValNo->id == 0 && "First value in interval is not 0?");
// Iterate over all of the blocks that the variable is completely
// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
// live interval.
- for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
- if (vi.AliveBlocks[i]) {
- LiveRange LR(getMBBStartIdx(i),
- getMBBEndIdx(i)+1, // MBB ends at -1.
- ValNo);
- interval.addRange(LR);
- DOUT << " +" << LR;
- }
+ for (int i = vi.AliveBlocks.find_first(); i != -1;
+ i = vi.AliveBlocks.find_next(i)) {
+ LiveRange LR(getMBBStartIdx(i),
+ getMBBEndIdx(i)+1, // MBB ends at -1.
+ ValNo);
+ interval.addRange(LR);
+ DOUT << " +" << LR;
}
// Finally, this virtual register is live from the start of any killing
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(interval.reg, MOIdx)) {
+ if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
assert(interval.containsOneValue());
unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
unsigned RedefIndex = getDefIndex(MIIdx);
+ if (MO.isEarlyClobber())
+ RedefIndex = getUseIndex(MIIdx);
const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
VNInfo *OldValNo = OldLR->valno;
// Value#0 is now defined by the 2-addr instruction.
OldValNo->def = RedefIndex;
OldValNo->copy = 0;
+ if (MO.isEarlyClobber())
+ OldValNo->redefByEC = true;
// Add the new live interval which replaces the range for the input copy.
LiveRange LR(DefIndex, RedefIndex, ValNo);
// live until the end of the block. We've already taken care of the
// rest of the live range.
unsigned defIndex = getDefIndex(MIIdx);
+ if (MO.isEarlyClobber())
+ defIndex = getUseIndex(MIIdx);
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg;
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
- tii_->isMoveInstr(*mi, SrcReg, DstReg))
+ tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
unsigned baseIndex = MIIdx;
unsigned start = getDefIndex(baseIndex);
+ // Earlyclobbers move back one.
+ if (MO.isEarlyClobber())
+ start = getUseIndex(MIIdx);
unsigned end = start;
// If it is not used after definition, it is considered dead at
// [defSlot(def), defSlot(def)+1)
if (MO.isDead()) {
DOUT << " dead";
- end = getDefIndex(start) + 1;
+ end = start + 1;
goto exit;
}
// it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
DOUT << " dead";
- end = getDefIndex(start) + 1;
+ end = start + 1;
goto exit;
}
// instruction where we know it's dead is if it is live-in to the function
// and never used.
assert(!CopyMI && "physreg was not killed in defining block!");
- end = getDefIndex(start) + 1; // It's dead.
+ end = start + 1;
exit:
assert(start < end && "did not find end of interval?");
// Already exists? Extend old live interval.
LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
- VNInfo *ValNo = (OldLR != interval.end())
+ bool Extend = OldLR != interval.end();
+ VNInfo *ValNo = Extend
? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
+ if (MO.isEarlyClobber() && Extend)
+ ValNo->redefByEC = true;
LiveRange LR(start, end, ValNo);
interval.addRange(LR);
interval.addKill(LR.valno, end);
getOrCreateInterval(MO.getReg()));
else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg;
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
- tii_->isMoveInstr(*MI, SrcReg, DstReg))
+ tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = MI;
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()), CopyMI);
MachineBasicBlock::iterator mi = MBB->begin();
unsigned baseIndex = MIIdx;
unsigned start = baseIndex;
- unsigned end = start;
+ while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(baseIndex) == 0)
+ baseIndex += InstrSlots::NUM;
+ unsigned end = baseIndex;
+ bool SeenDefUse = false;
+
while (mi != MBB->end()) {
if (mi->killsRegister(interval.reg, tri_)) {
DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
+ SeenDefUse = true;
goto exit;
} else if (mi->modifiesRegister(interval.reg, tri_)) {
// Another instruction redefines the register before it is ever read.
// [defSlot(def), defSlot(def)+1)
DOUT << " dead";
end = getDefIndex(start) + 1;
+ SeenDefUse = true;
goto exit;
}
baseIndex += InstrSlots::NUM;
- while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
- getInstructionFromIndex(baseIndex) == 0)
- baseIndex += InstrSlots::NUM;
++mi;
+ if (mi != MBB->end()) {
+ while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(baseIndex) == 0)
+ baseIndex += InstrSlots::NUM;
+ }
}
exit:
// Live-in register might not be used at all.
- if (end == MIIdx) {
+ if (!SeenDefUse) {
if (isAlias) {
DOUT << " dead";
end = getDefIndex(MIIdx) + 1;
}
}
- LiveRange LR(start, end, interval.getNextValue(start, 0, VNInfoAllocator));
+ LiveRange LR(start, end, interval.getNextValue(~0U, 0, VNInfoAllocator));
interval.addRange(LR);
interval.addKill(LR.valno, end);
DOUT << " +" << LR << '\n';
/// registers. for some ordering of the machine instructions [1,N] a
/// live interval is an interval [i, j) where 1 <= i <= j < N for
/// which a variable is live
-void LiveIntervals::computeIntervals() {
+void LiveIntervals::computeIntervals() {
+
DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
<< "********** Function: "
<< ((Value*)mf_->getFunction())->getName() << '\n';
- // Track the index of the current machine instr.
- unsigned MIIndex = 0;
-
- // Skip over empty initial indices.
- while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
- getInstructionFromIndex(MIIndex) == 0)
- MIIndex += InstrSlots::NUM;
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
+ // Track the index of the current machine instr.
+ unsigned MIIndex = getMBBStartIdx(MBB);
DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
true);
}
+ // Skip over empty initial indices.
+ while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(MIIndex) == 0)
+ MIIndex += InstrSlots::NUM;
+
for (; MI != miEnd; ++MI) {
DOUT << MIIndex << "\t" << *MI;
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
- if (MO.isRegister() && MO.getReg() && MO.isDef())
+ if (MO.isReg() && MO.getReg() && MO.isDef()) {
handleRegisterDef(MBB, MI, MIIndex, MO, i);
+ }
}
-
- MIIndex += InstrSlots::NUM;
+
+ // Skip over the empty slots after each instruction.
+ unsigned Slots = MI->getDesc().getNumDefs();
+ if (Slots == 0)
+ Slots = 1;
+ MIIndex += InstrSlots::NUM * Slots;
// Skip over empty indices.
while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
}
}
-bool LiveIntervals::findLiveInMBBs(const LiveRange &LR,
+bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), LR.start);
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
bool ResVal = false;
while (I != Idx2MBBMap.end()) {
- if (LR.end <= I->first)
+ if (I->first >= End)
break;
MBBs.push_back(I->second);
ResVal = true;
return ResVal;
}
+bool LiveIntervals::findReachableMBBs(unsigned Start, unsigned End,
+ SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
+
+ bool ResVal = false;
+ while (I != Idx2MBBMap.end()) {
+ if (I->first > End)
+ break;
+ MachineBasicBlock *MBB = I->second;
+ if (getMBBEndIdx(MBB) > End)
+ break;
+ for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
+ SE = MBB->succ_end(); SI != SE; ++SI)
+ MBBs.push_back(*SI);
+ ResVal = true;
+ ++I;
+ }
+ return ResVal;
+}
+
+LiveInterval* LiveIntervals::createInterval(unsigned reg) {
+ float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
+ return new LiveInterval(reg, Weight);
+}
-LiveInterval LiveIntervals::createInterval(unsigned reg) {
- float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
- HUGE_VALF : 0.0F;
- return LiveInterval(reg, Weight);
+/// dupInterval - Duplicate a live interval. The caller is responsible for
+/// managing the allocated memory.
+LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
+ LiveInterval *NewLI = createInterval(li->reg);
+ NewLI->Copy(*li, getVNInfoAllocator());
+ return NewLI;
}
/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
if (!VNI->copy)
return 0;
- if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
- return VNI->copy->getOperand(1).getReg();
- if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
+ if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
+ // If it's extracting out of a physical register, return the sub-register.
+ unsigned Reg = VNI->copy->getOperand(1).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
+ Reg = tri_->getSubReg(Reg, VNI->copy->getOperand(2).getImm());
+ return Reg;
+ } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
return VNI->copy->getOperand(2).getReg();
- unsigned SrcReg, DstReg;
- if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg))
+
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
return SrcReg;
assert(0 && "Unrecognized copy instruction!");
return 0;
unsigned RegOp = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || Reg == li.reg)
/// val# of the specified interval is re-materializable.
bool LiveIntervals::isReMaterializable(const LiveInterval &li,
const VNInfo *ValNo, MachineInstr *MI,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
bool &isLoad) {
if (DisableReMat)
return false;
if (!EnableAggressiveRemat)
return false;
- // If the instruction access memory but the memoperands have been lost,
+ // If the instruction accesses memory but the memoperands have been lost,
// we can't analyze it.
const TargetInstrDesc &TID = MI->getDesc();
if ((TID.mayLoad() || TID.mayStore()) && MI->memoperands_empty())
// If the instruction accesses memory and the memory could be non-constant,
// assume the instruction is not rematerializable.
- for (alist<MachineMemOperand>::const_iterator I = MI->memoperands_begin(),
- E = MI->memoperands_end(); I != E; ++I) {
+ for (std::list<MachineMemOperand>::const_iterator
+ I = MI->memoperands_begin(), E = MI->memoperands_end(); I != E; ++I){
const MachineMemOperand &MMO = *I;
if (MMO.isVolatile() || MMO.isStore())
return false;
MachineRegisterInfo::def_iterator I = mri_->def_begin(Reg),
E = mri_->def_end();
- // For the def, it should be the only def.
+ // For the def, it should be the only def of that register.
if (MO.isDef() && (next(I) != E || IsLiveIn))
return false;
else if (Reg != ImpUse)
return false;
}
- // For uses, there should be only one associate def.
+ // For the use, there should be only one associated def.
if (I != E && (next(I) != E || IsLiveIn))
return false;
}
if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
return false;
}
+
+ // If a register operand of the re-materialized instruction is going to
+ // be spilled next, then it's not legal to re-materialize this instruction.
+ for (unsigned i = 0, e = SpillIs.size(); i != e; ++i)
+ if (ImpUse == SpillIs[i]->reg)
+ return false;
}
return true;
}
+/// isReMaterializable - Returns true if the definition MI of the specified
+/// val# of the specified interval is re-materializable.
+bool LiveIntervals::isReMaterializable(const LiveInterval &li,
+ const VNInfo *ValNo, MachineInstr *MI) {
+ SmallVector<LiveInterval*, 4> Dummy1;
+ bool Dummy2;
+ return isReMaterializable(li, ValNo, MI, Dummy1, Dummy2);
+}
+
/// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable.
-bool LiveIntervals::isReMaterializable(const LiveInterval &li, bool &isLoad) {
+bool LiveIntervals::isReMaterializable(const LiveInterval &li,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ bool &isLoad) {
isLoad = false;
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
i != e; ++i) {
MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx);
bool DefIsLoad = false;
if (!ReMatDefMI ||
- !isReMaterializable(li, VNI, ReMatDefMI, DefIsLoad))
+ !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
return false;
isLoad |= DefIsLoad;
}
SmallVector<unsigned, 2> &Ops,
unsigned &MRInfo,
SmallVector<unsigned, 2> &FoldOps) {
- const TargetInstrDesc &TID = MI->getDesc();
-
MRInfo = 0;
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
unsigned OpIdx = Ops[i];
MRInfo |= (unsigned)VirtRegMap::isMod;
else {
// Filter out two-address use operand(s).
- if (!MO.isImplicit() &&
- TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
+ if (MI->isRegTiedToDefOperand(OpIdx)) {
MRInfo = VirtRegMap::isModRef;
continue;
}
// use operand. Make sure we rewrite that as well.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister())
+ if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
SmallVector<int, 4> &ReMatIds,
const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
- std::map<unsigned,unsigned> &MBBVRegsMap,
+ DenseMap<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
MachineBasicBlock *MBB = MI->getParent();
unsigned loopDepth = loopInfo->getLoopDepth(MBB);
RestartInstruction:
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
- if (!mop.isRegister())
+ if (!mop.isReg())
continue;
unsigned Reg = mop.getReg();
unsigned RegI = Reg;
Ops.push_back(i);
for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
const MachineOperand &MOj = MI->getOperand(j);
- if (!MOj.isRegister())
+ if (!MOj.isReg())
continue;
unsigned RegJ = MOj.getReg();
if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
if (!TrySplit)
SSWeight += Weight;
+ // Create a new virtual register for the spill interval.
+ // Create the new register now so we can map the fold instruction
+ // to the new register so when it is unfolded we get the correct
+ // answer.
+ bool CreatedNewVReg = false;
+ if (NewVReg == 0) {
+ NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ CreatedNewVReg = true;
+ }
+
if (!TryFold)
CanFold = false;
else {
// optimal point to insert a load / store later.
if (!TrySplit) {
if (tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
- Ops, FoldSS, FoldSlot, Reg)) {
+ Ops, FoldSS, FoldSlot, NewVReg)) {
// Folding the load/store can completely change the instruction in
// unpredictable ways, rescan it from the beginning.
+
+ if (FoldSS) {
+ // We need to give the new vreg the same stack slot as the
+ // spilled interval.
+ vrm.assignVirt2StackSlot(NewVReg, FoldSlot);
+ }
+
HasUse = false;
HasDef = false;
CanFold = false;
}
}
- // Create a new virtual register for the spill interval.
- bool CreatedNewVReg = false;
- if (NewVReg == 0) {
- NewVReg = mri_->createVirtualRegister(rc);
- vrm.grow();
- CreatedNewVReg = true;
- }
mop.setReg(NewVReg);
if (mop.isImplicit())
rewriteImplicitOps(li, MI, NewVReg, vrm);
SmallVector<int, 4> &ReMatIds,
const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
- std::map<unsigned, std::vector<SRInfo> > &SpillIdxes,
+ DenseMap<unsigned, std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
- std::map<unsigned, std::vector<SRInfo> > &RestoreIdxes,
- std::map<unsigned,unsigned> &MBBVRegsMap,
+ DenseMap<unsigned, std::vector<SRInfo> > &RestoreIdxes,
+ DenseMap<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
bool AllCanFold = true;
unsigned NewVReg = 0;
unsigned MBBId = MBB->getNumber();
unsigned ThisVReg = 0;
if (TrySplit) {
- std::map<unsigned,unsigned>::const_iterator NVI = MBBVRegsMap.find(MBBId);
+ DenseMap<unsigned,unsigned>::iterator NVI = MBBVRegsMap.find(MBBId);
if (NVI != MBBVRegsMap.end()) {
ThisVReg = NVI->second;
// One common case:
if (VNI)
HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index));
}
- std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator SII =
SpillIdxes.find(MBBId);
if (!HasKill) {
if (SII == SpillIdxes.end()) {
}
if (HasUse) {
- std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator SII =
SpillIdxes.find(MBBId);
if (SII != SpillIdxes.end() &&
SII->second.back().vreg == NewVReg &&
(int)index > SII->second.back().index)
// Use(s) following the last def, it's not safe to fold the spill.
SII->second.back().canFold = false;
- std::map<unsigned, std::vector<SRInfo> >::iterator RII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator RII =
RestoreIdxes.find(MBBId);
if (RII != RestoreIdxes.end() && RII->second.back().vreg == NewVReg)
// If we are splitting live intervals, only fold if it's the first
bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
- std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return false;
std::vector<SRInfo> &Restores = RestoreIdxes[Id];
void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
- std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return;
std::vector<SRInfo> &Restores = RestoreIdxes[Id];
}
}
+namespace {
+ struct LISorter {
+ bool operator()(LiveInterval* A, LiveInterval* B) {
+ return A->beginNumber() < B->beginNumber();
+ }
+ };
+}
+
+std::vector<LiveInterval*> LiveIntervals::
+addIntervalsForSpillsFast(const LiveInterval &li,
+ const MachineLoopInfo *loopInfo,
+ VirtRegMap &vrm, float& SSWeight) {
+ unsigned slot = vrm.assignVirt2StackSlot(li.reg);
+
+ std::vector<LiveInterval*> added;
+
+ assert(li.weight != HUGE_VALF &&
+ "attempt to spill already spilled interval!");
+
+ DOUT << "\t\t\t\tadding intervals for spills for interval: ";
+ DEBUG(li.dump());
+ DOUT << '\n';
+
+ const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
+
+ SSWeight = 0.0f;
+
+ MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg);
+ while (RI != mri_->reg_end()) {
+ MachineInstr* MI = &*RI;
+
+ SmallVector<unsigned, 2> Indices;
+ bool HasUse = false;
+ bool HasDef = false;
+
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& mop = MI->getOperand(i);
+ if (!mop.isReg() || mop.getReg() != li.reg) continue;
+
+ HasUse |= MI->getOperand(i).isUse();
+ HasDef |= MI->getOperand(i).isDef();
+
+ Indices.push_back(i);
+ }
+
+ if (!tryFoldMemoryOperand(MI, vrm, NULL, getInstructionIndex(MI),
+ Indices, true, slot, li.reg)) {
+ unsigned NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ vrm.assignVirt2StackSlot(NewVReg, slot);
+
+ // create a new register for this spill
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+
+ // the spill weight is now infinity as it
+ // cannot be spilled again
+ nI.weight = HUGE_VALF;
+
+ // Rewrite register operands to use the new vreg.
+ for (SmallVectorImpl<unsigned>::iterator I = Indices.begin(),
+ E = Indices.end(); I != E; ++I) {
+ MI->getOperand(*I).setReg(NewVReg);
+
+ if (MI->getOperand(*I).isUse())
+ MI->getOperand(*I).setIsKill(true);
+ }
+
+ // Fill in the new live interval.
+ unsigned index = getInstructionIndex(MI);
+ if (HasUse) {
+ LiveRange LR(getLoadIndex(index), getUseIndex(index),
+ nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ vrm.addRestorePoint(NewVReg, MI);
+ }
+ if (HasDef) {
+ LiveRange LR(getDefIndex(index), getStoreIndex(index),
+ nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ vrm.addSpillPoint(NewVReg, true, MI);
+ }
+
+ added.push_back(&nI);
+
+ DOUT << "\t\t\t\tadded new interval: ";
+ DEBUG(nI.dump());
+ DOUT << '\n';
+
+ unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
+ if (HasUse) {
+ if (HasDef)
+ SSWeight += getSpillWeight(true, true, loopDepth);
+ else
+ SSWeight += getSpillWeight(false, true, loopDepth);
+ } else
+ SSWeight += getSpillWeight(true, false, loopDepth);
+ }
+
+
+ RI = mri_->reg_begin(li.reg);
+ }
+
+ // Clients expect the new intervals to be returned in sorted order.
+ std::sort(added.begin(), added.end(), LISorter());
+
+ return added;
+}
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
float &SSWeight) {
+
+ if (EnableFastSpilling)
+ return addIntervalsForSpillsFast(li, loopInfo, vrm, SSWeight);
+
assert(li.weight != HUGE_VALF &&
"attempt to spill already spilled interval!");
// Spill slot weight.
SSWeight = 0.0f;
- // Each bit specify whether it a spill is required in the MBB.
+ // Each bit specify whether a spill is required in the MBB.
BitVector SpillMBBs(mf_->getNumBlockIDs());
- std::map<unsigned, std::vector<SRInfo> > SpillIdxes;
+ DenseMap<unsigned, std::vector<SRInfo> > SpillIdxes;
BitVector RestoreMBBs(mf_->getNumBlockIDs());
- std::map<unsigned, std::vector<SRInfo> > RestoreIdxes;
- std::map<unsigned,unsigned> MBBVRegsMap;
+ DenseMap<unsigned, std::vector<SRInfo> > RestoreIdxes;
+ DenseMap<unsigned,unsigned> MBBVRegsMap;
std::vector<LiveInterval*> NewLIs;
const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
+ (DefIsReMat && (ReMatDefMI->getDesc().canFoldAsLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
MachineInstr *ReMatDefMI = (DefIdx == ~0u)
? 0 : getInstructionFromIndex(DefIdx);
bool dummy;
- if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, dummy)) {
+ if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, SpillIs, dummy)) {
// Remember how to remat the def of this val#.
ReMatOrigDefs[VN] = ReMatDefMI;
// Original def may be modified so we have to make a copy here.
}
// One stack slot per live interval.
- if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0)
- Slot = vrm.assignVirt2StackSlot(li.reg);
+ if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0) {
+ if (vrm.getStackSlot(li.reg) == VirtRegMap::NO_STACK_SLOT)
+ Slot = vrm.assignVirt2StackSlot(li.reg);
+
+ // This case only occurs when the prealloc splitter has already assigned
+ // a stack slot to this vreg.
+ else
+ Slot = vrm.getStackSlot(li.reg);
+ }
// Create new intervals and rewrite defs and uses.
for (LiveInterval::Ranges::const_iterator
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
+ (DefIsReMat && ReMatDefMI->getDesc().canFoldAsLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo,
CanFold = true;
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
MachineOperand &MO = MI->getOperand(j);
- if (!MO.isRegister() || MO.getReg() != VReg)
+ if (!MO.isReg() || MO.getReg() != VReg)
continue;
Ops.push_back(j);
if (CanFold && !Ops.empty()) {
if (tryFoldMemoryOperand(MI, vrm, NULL, index, Ops, true, Slot,VReg)){
Folded = true;
- if (FoundUse > 0) {
+ if (FoundUse) {
// Also folded uses, do not issue a load.
eraseRestoreInfo(Id, index, VReg, RestoreMBBs, RestoreIdxes);
nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
CanFold = true;
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
MachineOperand &MO = MI->getOperand(j);
- if (!MO.isRegister() || MO.getReg() != VReg)
+ if (!MO.isReg() || MO.getReg() != VReg)
continue;
if (MO.isDef()) {
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
- if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
+ if (isLoadSS || ReMatDefMI->getDesc().canFoldAsLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
- unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
- if (ImpUse) {
- // Re-matting an instruction with virtual register use. Add the
- // register as an implicit use on the use MI and update the register
- // interval's spill weight to HUGE_VALF to prevent it from being
- // spilled.
- LiveInterval &ImpLi = getInterval(ImpUse);
- ImpLi.weight = HUGE_VALF;
- MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+ if (!Folded) {
+ unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
+ if (ImpUse) {
+ // Re-matting an instruction with virtual register use. Add the
+ // register as an implicit use on the use MI and update the register
+ // interval's spill weight to HUGE_VALF to prevent it from being
+ // spilled.
+ LiveInterval &ImpLi = getInterval(ImpUse);
+ ImpLi.weight = HUGE_VALF;
+ MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+ }
}
}
}
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false);
assert(UseIdx != -1);
- if (LastUse->getOperand(UseIdx).isImplicit() ||
- LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){
+ if (!LastUse->isRegTiedToDefOperand(UseIdx)) {
LastUse->getOperand(UseIdx).setIsKill();
vrm.addKillPoint(LI->reg, LastUseIdx);
}
}
/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
-/// around all defs and uses of the specified interval.
-void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
+/// around all defs and uses of the specified interval. Return true if it
+/// was able to cut its interval.
+bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
unsigned PhysReg, VirtRegMap &vrm) {
unsigned SpillReg = getRepresentativeReg(PhysReg);
assert(*AS == SpillReg || !allocatableRegs_[*AS] ||
tri_->isSuperRegister(*AS, SpillReg));
+ bool Cut = false;
LiveInterval &pli = getInterval(SpillReg);
SmallPtrSet<MachineInstr*, 8> SeenMIs;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
unsigned Index = getInstructionIndex(MI);
if (pli.liveAt(Index)) {
vrm.addEmergencySpill(SpillReg, MI);
- pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
+ unsigned StartIdx = getLoadIndex(Index);
+ unsigned EndIdx = getStoreIndex(Index)+1;
+ if (pli.isInOneLiveRange(StartIdx, EndIdx)) {
+ pli.removeRange(StartIdx, EndIdx);
+ Cut = true;
+ } else {
+ cerr << "Ran out of registers during register allocation!\n";
+ if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+ cerr << "Please check your inline asm statement for invalid "
+ << "constraints:\n";
+ MI->print(cerr.stream(), tm_);
+ }
+ exit(1);
+ }
for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
if (!hasInterval(*AS))
continue;
}
}
}
+ return Cut;
}
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
projects / oota-llvm.git / blobdiff