-//===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===//
+//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
//
// The LLVM Compiler Infrastructure
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "liveintervals"
-#include "LiveIntervals.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "VirtRegMap.h"
#include "llvm/Value.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/CommandLine.h"
-#include "Support/Debug.h"
-#include "Support/Statistic.h"
-#include "Support/STLExtras.h"
-#include "VirtRegMap.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+#include <algorithm>
#include <cmath>
#include <iostream>
-
using namespace llvm;
namespace {
- RegisterAnalysis<LiveIntervals> X("liveintervals",
- "Live Interval Analysis");
+ RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
- Statistic<> numIntervals
- ("liveintervals", "Number of original intervals");
+ Statistic<> numIntervals
+ ("liveintervals", "Number of original intervals");
- Statistic<> numIntervalsAfter
- ("liveintervals", "Number of intervals after coalescing");
+ Statistic<> numIntervalsAfter
+ ("liveintervals", "Number of intervals after coalescing");
- Statistic<> numJoins
- ("liveintervals", "Number of interval joins performed");
+ Statistic<> numJoins
+ ("liveintervals", "Number of interval joins performed");
- Statistic<> numPeep
- ("liveintervals", "Number of identity moves eliminated after coalescing");
+ Statistic<> numPeep
+ ("liveintervals", "Number of identity moves eliminated after coalescing");
- Statistic<> numFolded
- ("liveintervals", "Number of loads/stores folded into instructions");
+ Statistic<> numFolded
+ ("liveintervals", "Number of loads/stores folded into instructions");
- cl::opt<bool>
- join("join-liveintervals",
- cl::desc("Join compatible live intervals"),
- cl::init(false));
-};
+ cl::opt<bool>
+ EnableJoining("join-liveintervals",
+ cl::desc("Join compatible live intervals"),
+ cl::init(true));
+}
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
- AU.addPreserved<LiveVariables>();
- AU.addRequired<LiveVariables>();
- AU.addPreservedID(PHIEliminationID);
- AU.addRequiredID(PHIEliminationID);
- AU.addRequiredID(TwoAddressInstructionPassID);
- AU.addRequired<LoopInfo>();
- MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<LiveVariables>();
+ AU.addPreservedID(PHIEliminationID);
+ AU.addRequiredID(PHIEliminationID);
+ AU.addRequiredID(TwoAddressInstructionPassID);
+ AU.addRequired<LoopInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
}
void LiveIntervals::releaseMemory()
{
- mbbi2mbbMap_.clear();
- mi2iMap_.clear();
- i2miMap_.clear();
- r2iMap_.clear();
- r2rMap_.clear();
- intervals_.clear();
+ mi2iMap_.clear();
+ i2miMap_.clear();
+ r2iMap_.clear();
+ r2rMap_.clear();
+}
+
+
+static bool isZeroLengthInterval(LiveInterval *li) {
+ for (LiveInterval::Ranges::const_iterator
+ i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
+ if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
+ return false;
+ return true;
}
/// runOnMachineFunction - Register allocate the whole function
///
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
- mf_ = &fn;
- tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
- lv_ = &getAnalysis<LiveVariables>();
-
- // number MachineInstrs
- unsigned miIndex = 0;
- for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
- mbb != mbbEnd; ++mbb) {
- unsigned mbbIdx = mbb->getNumber();
- bool inserted = mbbi2mbbMap_.insert(std::make_pair(mbbIdx,
- mbb)).second;
- assert(inserted && "multiple index -> MachineBasicBlock");
-
- for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
- mi != miEnd; ++mi) {
- inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
- assert(inserted && "multiple MachineInstr -> index mappings");
- i2miMap_.push_back(mi);
- miIndex += InstrSlots::NUM;
- }
+ mf_ = &fn;
+ tm_ = &fn.getTarget();
+ mri_ = tm_->getRegisterInfo();
+ tii_ = tm_->getInstrInfo();
+ lv_ = &getAnalysis<LiveVariables>();
+ allocatableRegs_ = mri_->getAllocatableSet(fn);
+ r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
+
+ // If this function has any live ins, insert a dummy instruction at the
+ // beginning of the function that we will pretend "defines" the values. This
+ // is to make the interval analysis simpler by providing a number.
+ if (fn.livein_begin() != fn.livein_end()) {
+ unsigned FirstLiveIn = fn.livein_begin()->first;
+
+ // Find a reg class that contains this live in.
+ const TargetRegisterClass *RC = 0;
+ for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
+ E = mri_->regclass_end(); RCI != E; ++RCI)
+ if ((*RCI)->contains(FirstLiveIn)) {
+ RC = *RCI;
+ break;
+ }
+
+ MachineInstr *OldFirstMI = fn.begin()->begin();
+ mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
+ FirstLiveIn, FirstLiveIn, RC);
+ assert(OldFirstMI != fn.begin()->begin() &&
+ "copyRetToReg didn't insert anything!");
+ }
+
+ // number MachineInstrs
+ unsigned miIndex = 0;
+ for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
+ mbb != mbbEnd; ++mbb)
+ for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
+ mi != miEnd; ++mi) {
+ bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
+ assert(inserted && "multiple MachineInstr -> index mappings");
+ i2miMap_.push_back(mi);
+ miIndex += InstrSlots::NUM;
}
- computeIntervals();
-
- numIntervals += intervals_.size();
-
- // join intervals if requested
- if (join) joinIntervals();
-
- numIntervalsAfter += intervals_.size();
-
- // perform a final pass over the instructions and compute spill
- // weights, coalesce virtual registers and remove identity moves
- const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
- const TargetInstrInfo& tii = *tm_->getInstrInfo();
-
- for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
- mbbi != mbbe; ++mbbi) {
- MachineBasicBlock* mbb = mbbi;
- unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
-
- for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
- mii != mie; ) {
- // if the move will be an identity move delete it
- unsigned srcReg, dstReg;
- if (tii.isMoveInstr(*mii, srcReg, dstReg) &&
- rep(srcReg) == rep(dstReg)) {
- // remove from def list
- LiveInterval& interval = getOrCreateInterval(rep(dstReg));
- // remove index -> MachineInstr and
- // MachineInstr -> index mappings
- Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
- if (mi2i != mi2iMap_.end()) {
- i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
- mi2iMap_.erase(mi2i);
- }
- mii = mbbi->erase(mii);
- ++numPeep;
- }
- else {
- for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
- const MachineOperand& mop = mii->getOperand(i);
- if (mop.isRegister() && mop.getReg() &&
- MRegisterInfo::isVirtualRegister(mop.getReg())) {
- // replace register with representative register
- unsigned reg = rep(mop.getReg());
- mii->SetMachineOperandReg(i, reg);
-
- Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
- assert(r2iit != r2iMap_.end());
- r2iit->second->weight +=
- (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth);
- }
- }
- ++mii;
- }
- }
+ // Note intervals due to live-in values.
+ if (fn.livein_begin() != fn.livein_end()) {
+ MachineBasicBlock *Entry = fn.begin();
+ for (MachineFunction::livein_iterator I = fn.livein_begin(),
+ E = fn.livein_end(); I != E; ++I) {
+ handlePhysicalRegisterDef(Entry, Entry->begin(),
+ getOrCreateInterval(I->first), 0, 0, true);
+ for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
+ handlePhysicalRegisterDef(Entry, Entry->begin(),
+ getOrCreateInterval(*AS), 0, 0, true);
}
+ }
+
+ computeIntervals();
- intervals_.sort();
- DEBUG(std::cerr << "********** INTERVALS **********\n");
- DEBUG(std::copy(intervals_.begin(), intervals_.end(),
- std::ostream_iterator<LiveInterval>(std::cerr, "\n")));
- DEBUG(std::cerr << "********** MACHINEINSTRS **********\n");
- DEBUG(
- for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
- mbbi != mbbe; ++mbbi) {
- std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
- for (MachineBasicBlock::iterator mii = mbbi->begin(),
- mie = mbbi->end(); mii != mie; ++mii) {
- std::cerr << getInstructionIndex(mii) << '\t';
- mii->print(std::cerr, tm_);
- }
+ numIntervals += getNumIntervals();
+
+ DEBUG(std::cerr << "********** INTERVALS **********\n";
+ for (iterator I = begin(), E = end(); I != E; ++I) {
+ I->second.print(std::cerr, mri_);
+ std::cerr << "\n";
});
- return true;
+ // join intervals if requested
+ if (EnableJoining) joinIntervals();
+
+ numIntervalsAfter += getNumIntervals();
+
+ // perform a final pass over the instructions and compute spill
+ // weights, coalesce virtual registers and remove identity moves
+ const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
+
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ MachineBasicBlock* mbb = mbbi;
+ unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
+
+ for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
+ mii != mie; ) {
+ // if the move will be an identity move delete it
+ unsigned srcReg, dstReg, RegRep;
+ if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
+ (RegRep = rep(srcReg)) == rep(dstReg)) {
+ // remove from def list
+ LiveInterval &interval = getOrCreateInterval(RegRep);
+ // remove index -> MachineInstr and
+ // MachineInstr -> index mappings
+ Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
+ if (mi2i != mi2iMap_.end()) {
+ i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
+ mi2iMap_.erase(mi2i);
+ }
+ mii = mbbi->erase(mii);
+ ++numPeep;
+ }
+ else {
+ for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
+ const MachineOperand& mop = mii->getOperand(i);
+ if (mop.isRegister() && mop.getReg() &&
+ MRegisterInfo::isVirtualRegister(mop.getReg())) {
+ // replace register with representative register
+ unsigned reg = rep(mop.getReg());
+ mii->getOperand(i).setReg(reg);
+
+ LiveInterval &RegInt = getInterval(reg);
+ RegInt.weight +=
+ (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
+ }
+ }
+ ++mii;
+ }
+ }
+ }
+
+ for (iterator I = begin(), E = end(); I != E; ++I) {
+ LiveInterval &li = I->second;
+ if (MRegisterInfo::isVirtualRegister(li.reg))
+ // If the live interval legnth is essentially zero, i.e. in every live
+ // range the use follows def immediately, it doesn't make sense to spill
+ // it and hope it will be easier to allocate for this li.
+ if (isZeroLengthInterval(&li))
+ li.weight = float(HUGE_VAL);
+ }
+
+ DEBUG(dump());
+ return true;
}
-std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
- const LiveInterval& li,
- VirtRegMap& vrm,
- int slot)
-{
- std::vector<LiveInterval*> added;
-
- assert(li.weight != HUGE_VAL &&
- "attempt to spill already spilled interval!");
-
- DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
- << li << '\n');
-
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
-
- for (LiveInterval::Ranges::const_iterator
- i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
- unsigned index = getBaseIndex(i->first);
- unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM;
- for (; index < end; index += InstrSlots::NUM) {
- // skip deleted instructions
- while (!getInstructionFromIndex(index)) index += InstrSlots::NUM;
- MachineBasicBlock::iterator mi = getInstructionFromIndex(index);
-
- for_operand:
- for (unsigned i = 0; i < mi->getNumOperands(); ++i) {
- MachineOperand& mop = mi->getOperand(i);
- if (mop.isRegister() && mop.getReg() == li.reg) {
- if (MachineInstr* fmi =
- mri_->foldMemoryOperand(mi, i, slot)) {
- lv_->instructionChanged(mi, fmi);
- vrm.virtFolded(li.reg, mi, fmi);
- mi2iMap_.erase(mi);
- i2miMap_[index/InstrSlots::NUM] = fmi;
- mi2iMap_[fmi] = index;
- MachineBasicBlock& mbb = *mi->getParent();
- mi = mbb.insert(mbb.erase(mi), fmi);
- ++numFolded;
- goto for_operand;
- }
- else {
- // This is tricky. We need to add information in
- // the interval about the spill code so we have to
- // use our extra load/store slots.
- //
- // If we have a use we are going to have a load so
- // we start the interval from the load slot
- // onwards. Otherwise we start from the def slot.
- unsigned start = (mop.isUse() ?
- getLoadIndex(index) :
- getDefIndex(index));
- // If we have a def we are going to have a store
- // right after it so we end the interval after the
- // use of the next instruction. Otherwise we end
- // after the use of this instruction.
- unsigned end = 1 + (mop.isDef() ?
- getUseIndex(index+InstrSlots::NUM) :
- getUseIndex(index));
-
- // create a new register for this spill
- unsigned nReg =
- mf_->getSSARegMap()->createVirtualRegister(rc);
- mi->SetMachineOperandReg(i, nReg);
- vrm.grow();
- vrm.assignVirt2StackSlot(nReg, slot);
- LiveInterval& nI = getOrCreateInterval(nReg);
- assert(nI.empty());
- // the spill weight is now infinity as it
- // cannot be spilled again
- nI.weight = HUGE_VAL;
- nI.addRange(start, end);
- added.push_back(&nI);
- // update live variables
- lv_->addVirtualRegisterKilled(nReg, mi->getParent(),mi);
- DEBUG(std::cerr << "\t\t\t\tadded new interval: "
- << nI << '\n');
- }
- }
- }
+/// print - Implement the dump method.
+void LiveIntervals::print(std::ostream &O, const Module* ) const {
+ O << "********** INTERVALS **********\n";
+ for (const_iterator I = begin(), E = end(); I != E; ++I) {
+ I->second.print(std::cerr, mri_);
+ std::cerr << "\n";
+ }
+
+ O << "********** MACHINEINSTRS **********\n";
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
+ for (MachineBasicBlock::iterator mii = mbbi->begin(),
+ mie = mbbi->end(); mii != mie; ++mii) {
+ O << getInstructionIndex(mii) << '\t' << *mii;
+ }
+ }
+}
+
+std::vector<LiveInterval*> LiveIntervals::
+addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
+ // since this is called after the analysis is done we don't know if
+ // LiveVariables is available
+ lv_ = getAnalysisToUpdate<LiveVariables>();
+
+ std::vector<LiveInterval*> added;
+
+ assert(li.weight != HUGE_VAL &&
+ "attempt to spill already spilled interval!");
+
+ DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
+ << li << '\n');
+
+ const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
+
+ for (LiveInterval::Ranges::const_iterator
+ i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
+ unsigned index = getBaseIndex(i->start);
+ unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
+ for (; index != end; index += InstrSlots::NUM) {
+ // skip deleted instructions
+ while (index != end && !getInstructionFromIndex(index))
+ index += InstrSlots::NUM;
+ if (index == end) break;
+
+ MachineInstr *MI = getInstructionFromIndex(index);
+
+ // NewRegLiveIn - This instruction might have multiple uses of the spilled
+ // register. In this case, for the first use, keep track of the new vreg
+ // that we reload it into. If we see a second use, reuse this vreg
+ // instead of creating live ranges for two reloads.
+ unsigned NewRegLiveIn = 0;
+
+ for_operand:
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& mop = MI->getOperand(i);
+ if (mop.isRegister() && mop.getReg() == li.reg) {
+ if (NewRegLiveIn && mop.isUse()) {
+ // We already emitted a reload of this value, reuse it for
+ // subsequent operands.
+ MI->getOperand(i).setReg(NewRegLiveIn);
+ DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
+ << " for operand #" << i << '\n');
+ } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
+ // Attempt to fold the memory reference into the instruction. If we
+ // can do this, we don't need to insert spill code.
+ if (lv_)
+ lv_->instructionChanged(MI, fmi);
+ MachineBasicBlock &MBB = *MI->getParent();
+ vrm.virtFolded(li.reg, MI, i, fmi);
+ mi2iMap_.erase(MI);
+ i2miMap_[index/InstrSlots::NUM] = fmi;
+ mi2iMap_[fmi] = index;
+ MI = MBB.insert(MBB.erase(MI), fmi);
+ ++numFolded;
+ // Folding the load/store can completely change the instruction in
+ // unpredictable ways, rescan it from the beginning.
+ goto for_operand;
+ } else {
+ // This is tricky. We need to add information in the interval about
+ // the spill code so we have to use our extra load/store slots.
+ //
+ // If we have a use we are going to have a load so we start the
+ // interval from the load slot onwards. Otherwise we start from the
+ // def slot.
+ unsigned start = (mop.isUse() ?
+ getLoadIndex(index) :
+ getDefIndex(index));
+ // If we have a def we are going to have a store right after it so
+ // we end the interval after the use of the next
+ // instruction. Otherwise we end after the use of this instruction.
+ unsigned end = 1 + (mop.isDef() ?
+ getStoreIndex(index) :
+ getUseIndex(index));
+
+ // create a new register for this spill
+ NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
+ MI->getOperand(i).setReg(NewRegLiveIn);
+ vrm.grow();
+ vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
+ LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
+ assert(nI.empty());
+
+ // the spill weight is now infinity as it
+ // cannot be spilled again
+ nI.weight = float(HUGE_VAL);
+ LiveRange LR(start, end, nI.getNextValue());
+ DEBUG(std::cerr << " +" << LR);
+ nI.addRange(LR);
+ added.push_back(&nI);
+
+ // update live variables if it is available
+ if (lv_)
+ lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
+
+ // If this is a live in, reuse it for subsequent live-ins. If it's
+ // a def, we can't do this.
+ if (!mop.isUse()) NewRegLiveIn = 0;
+
+ DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
+ }
}
+ }
}
+ }
- return added;
+ return added;
}
void LiveIntervals::printRegName(unsigned reg) const
{
- if (MRegisterInfo::isPhysicalRegister(reg))
- std::cerr << mri_->getName(reg);
- else
- std::cerr << "%reg" << reg;
+ if (MRegisterInfo::isPhysicalRegister(reg))
+ std::cerr << mri_->getName(reg);
+ else
+ std::cerr << "%reg" << reg;
}
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
MachineBasicBlock::iterator mi,
LiveInterval& interval)
{
- DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
- LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
+ DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
+
+ // Virtual registers may be defined multiple times (due to phi
+ // elimination and 2-addr elimination). Much of what we do only has to be
+ // done once for the vreg. We use an empty interval to detect the first
+ // time we see a vreg.
+ if (interval.empty()) {
+ // Get the Idx of the defining instructions.
+ unsigned defIndex = getDefIndex(getInstructionIndex(mi));
+
+ unsigned ValNum = interval.getNextValue();
+ assert(ValNum == 0 && "First value in interval is not 0?");
+ ValNum = 0; // Clue in the optimizer.
+
+ // Loop over all of the blocks that the vreg is defined in. There are
+ // two cases we have to handle here. The most common case is a vreg
+ // whose lifetime is contained within a basic block. In this case there
+ // will be a single kill, in MBB, which comes after the definition.
+ if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
+ // FIXME: what about dead vars?
+ unsigned killIdx;
+ if (vi.Kills[0] != mi)
+ killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
+ else
+ killIdx = defIndex+1;
+
+ // If the kill happens after the definition, we have an intra-block
+ // live range.
+ if (killIdx > defIndex) {
+ assert(vi.AliveBlocks.empty() &&
+ "Shouldn't be alive across any blocks!");
+ LiveRange LR(defIndex, killIdx, ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR << "\n");
+ return;
+ }
+ }
+
+ // The other case we handle is when a virtual register lives to the end
+ // of the defining block, potentially live across some blocks, then is
+ // live into some number of blocks, but gets killed. Start by adding a
+ // range that goes from this definition to the end of the defining block.
+ LiveRange NewLR(defIndex,
+ getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
+ ValNum);
+ DEBUG(std::cerr << " +" << NewLR);
+ interval.addRange(NewLR);
// Iterate over all of the blocks that the variable is completely
// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
- // live interval. Obviously we only need to do this once.
- if (interval.empty()) {
- for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
- if (vi.AliveBlocks[i]) {
- MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
- if (!mbb->empty()) {
- interval.addRange(
- getInstructionIndex(&mbb->front()),
- getInstructionIndex(&mbb->back()) + InstrSlots::NUM);
- }
- }
+ // live interval.
+ for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
+ if (vi.AliveBlocks[i]) {
+ MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
+ if (!mbb->empty()) {
+ LiveRange LR(getInstructionIndex(&mbb->front()),
+ getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
+ ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR);
}
+ }
}
- unsigned baseIndex = getInstructionIndex(mi);
-
- bool killedInDefiningBasicBlock = false;
- for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
- MachineBasicBlock* killerBlock = vi.Kills[i].first;
- MachineInstr* killerInstr = vi.Kills[i].second;
- unsigned start = (mbb == killerBlock ?
- getDefIndex(baseIndex) :
- getInstructionIndex(&killerBlock->front()));
- unsigned end = (killerInstr == mi ?
- // dead
- start + 1 :
- // killed
- getUseIndex(getInstructionIndex(killerInstr))+1);
- // we do not want to add invalid ranges. these can happen when
- // a variable has its latest use and is redefined later on in
- // the same basic block (common with variables introduced by
- // PHI elimination)
- if (start < end) {
- killedInDefiningBasicBlock |= mbb == killerBlock;
- interval.addRange(start, end);
- }
+ // Finally, this virtual register is live from the start of any killing
+ // block to the 'use' slot of the killing instruction.
+ for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
+ MachineInstr *Kill = vi.Kills[i];
+ LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
+ getUseIndex(getInstructionIndex(Kill))+1,
+ ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR);
}
- if (!killedInDefiningBasicBlock) {
- unsigned end = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
- interval.addRange(getDefIndex(baseIndex), end);
+ } else {
+ // If this is the second time we see a virtual register definition, it
+ // must be due to phi elimination or two addr elimination. If this is
+ // the result of two address elimination, then the vreg is the first
+ // operand, and is a def-and-use.
+ if (mi->getOperand(0).isRegister() &&
+ mi->getOperand(0).getReg() == interval.reg &&
+ mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
+ // If this is a two-address definition, then we have already processed
+ // the live range. The only problem is that we didn't realize there
+ // are actually two values in the live interval. Because of this we
+ // need to take the LiveRegion that defines this register and split it
+ // into two values.
+ unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
+ unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
+
+ // Delete the initial value, which should be short and continuous,
+ // becuase the 2-addr copy must be in the same MBB as the redef.
+ interval.removeRange(DefIndex, RedefIndex);
+
+ LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
+ DEBUG(std::cerr << " replace range with " << LR);
+ interval.addRange(LR);
+
+ // If this redefinition is dead, we need to add a dummy unit live
+ // range covering the def slot.
+ if (lv_->RegisterDefIsDead(mi, interval.reg))
+ interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
+
+ DEBUG(std::cerr << "RESULT: " << interval);
+
+ } else {
+ // Otherwise, this must be because of phi elimination. If this is the
+ // first redefinition of the vreg that we have seen, go back and change
+ // the live range in the PHI block to be a different value number.
+ if (interval.containsOneValue()) {
+ assert(vi.Kills.size() == 1 &&
+ "PHI elimination vreg should have one kill, the PHI itself!");
+
+ // Remove the old range that we now know has an incorrect number.
+ MachineInstr *Killer = vi.Kills[0];
+ unsigned Start = getInstructionIndex(Killer->getParent()->begin());
+ unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
+ DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
+ << interval << "\n");
+ interval.removeRange(Start, End);
+ DEBUG(std::cerr << "RESULT: " << interval);
+
+ // Replace the interval with one of a NEW value number.
+ LiveRange LR(Start, End, interval.getNextValue());
+ DEBUG(std::cerr << " replace range with " << LR);
+ interval.addRange(LR);
+ DEBUG(std::cerr << "RESULT: " << interval);
+ }
+
+ // In the case of PHI elimination, each variable definition is only
+ // live until the end of the block. We've already taken care of the
+ // rest of the live range.
+ unsigned defIndex = getDefIndex(getInstructionIndex(mi));
+ LiveRange LR(defIndex,
+ getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
+ interval.getNextValue());
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR);
}
- DEBUG(std::cerr << '\n');
+ }
+
+ DEBUG(std::cerr << '\n');
}
-void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
+void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
- LiveInterval& interval)
+ LiveInterval& interval,
+ unsigned SrcReg, unsigned DestReg,
+ bool isLiveIn)
{
- // A physical register cannot be live across basic block, so its
- // lifetime must end somewhere in its defining basic block.
- DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
- typedef LiveVariables::killed_iterator KillIter;
-
- MachineBasicBlock::iterator e = mbb->end();
- unsigned baseIndex = getInstructionIndex(mi);
- unsigned start = getDefIndex(baseIndex);
- unsigned end = start;
-
- // If it is not used after definition, it is considered dead at
- // the instruction defining it. Hence its interval is:
- // [defSlot(def), defSlot(def)+1)
- for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
- ki != ke; ++ki) {
- if (interval.reg == ki->second) {
- DEBUG(std::cerr << " dead");
- end = getDefIndex(start) + 1;
- goto exit;
- }
+ // A physical register cannot be live across basic block, so its
+ // lifetime must end somewhere in its defining basic block.
+ DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
+ typedef LiveVariables::killed_iterator KillIter;
+
+ unsigned baseIndex = getInstructionIndex(mi);
+ unsigned start = getDefIndex(baseIndex);
+ unsigned end = start;
+
+ // If it is not used after definition, it is considered dead at
+ // the instruction defining it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ if (lv_->RegisterDefIsDead(mi, interval.reg)) {
+ DEBUG(std::cerr << " dead");
+ end = getDefIndex(start) + 1;
+ goto exit;
+ }
+
+ // If it is not dead on definition, it must be killed by a
+ // subsequent instruction. Hence its interval is:
+ // [defSlot(def), useSlot(kill)+1)
+ while (++mi != MBB->end()) {
+ baseIndex += InstrSlots::NUM;
+ if (lv_->KillsRegister(mi, interval.reg)) {
+ DEBUG(std::cerr << " killed");
+ end = getUseIndex(baseIndex) + 1;
+ goto exit;
}
-
- // If it is not dead on definition, it must be killed by a
- // subsequent instruction. Hence its interval is:
- // [defSlot(def), useSlot(def)+1)
- do {
- ++mi;
- baseIndex += InstrSlots::NUM;
- for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
- ki != ke; ++ki) {
- if (interval.reg == ki->second) {
- DEBUG(std::cerr << " killed");
- end = getUseIndex(baseIndex) + 1;
- goto exit;
- }
- }
- } while (mi != e);
+ }
+
+ // The only case we should have a dead physreg here without a killing or
+ // instruction where we know it's dead is if it is live-in to the function
+ // and never used.
+ assert(isLiveIn && "physreg was not killed in defining block!");
+ end = getDefIndex(start) + 1; // It's dead.
exit:
- assert(start < end && "did not find end of interval?");
- interval.addRange(start, end);
- DEBUG(std::cerr << '\n');
-}
-
-void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb,
- MachineBasicBlock::iterator mi,
- unsigned reg)
-{
- if (MRegisterInfo::isPhysicalRegister(reg)) {
- if (lv_->getAllocatablePhysicalRegisters()[reg]) {
- handlePhysicalRegisterDef(mbb, mi, getOrCreateInterval(reg));
- for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
- handlePhysicalRegisterDef(mbb, mi, getOrCreateInterval(*as));
+ assert(start < end && "did not find end of interval?");
+
+ // Finally, if this is defining a new range for the physical register, and if
+ // that physreg is just a copy from a vreg, and if THAT vreg was a copy from
+ // the physreg, then the new fragment has the same value as the one copied
+ // into the vreg.
+ if (interval.reg == DestReg && !interval.empty() &&
+ MRegisterInfo::isVirtualRegister(SrcReg)) {
+
+ // Get the live interval for the vreg, see if it is defined by a copy.
+ LiveInterval &SrcInterval = getOrCreateInterval(SrcReg);
+
+ if (SrcInterval.containsOneValue()) {
+ assert(!SrcInterval.empty() && "Can't contain a value and be empty!");
+
+ // Get the first index of the first range. Though the interval may have
+ // multiple liveranges in it, we only check the first.
+ unsigned StartIdx = SrcInterval.begin()->start;
+ MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx);
+
+ // Check to see if the vreg was defined by a copy instruction, and that
+ // the source was this physreg.
+ unsigned VRegSrcSrc, VRegSrcDest;
+ if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) &&
+ SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) {
+ // Okay, now we know that the vreg was defined by a copy from this
+ // physreg. Find the value number being copied and use it as the value
+ // for this range.
+ const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1);
+ if (DefRange) {
+ LiveRange LR(start, end, DefRange->ValId);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR << '\n');
+ return;
}
+ }
}
- else
- handleVirtualRegisterDef(mbb, mi, getOrCreateInterval(reg));
-}
+ }
-unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const
-{
- Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
- return (it == mi2iMap_.end() ?
- std::numeric_limits<unsigned>::max() :
- it->second);
+
+ LiveRange LR(start, end, interval.getNextValue());
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR << '\n');
}
-MachineInstr* LiveIntervals::getInstructionFromIndex(unsigned index) const
-{
- index /= InstrSlots::NUM; // convert index to vector index
- assert(index < i2miMap_.size() &&
- "index does not correspond to an instruction");
- return i2miMap_[index];
+void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned reg) {
+ if (MRegisterInfo::isVirtualRegister(reg))
+ handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
+ else if (allocatableRegs_[reg]) {
+ unsigned SrcReg = 0, DestReg = 0;
+ if (!tii_->isMoveInstr(*MI, SrcReg, DestReg))
+ SrcReg = DestReg = 0;
+
+ handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg),
+ SrcReg, DestReg);
+ for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
+ handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS),
+ SrcReg, DestReg);
+ }
}
/// computeIntervals - computes the live intervals for virtual
/// which a variable is live
void LiveIntervals::computeIntervals()
{
- DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
- DEBUG(std::cerr << "********** Function: "
- << ((Value*)mf_->getFunction())->getName() << '\n');
-
- for (MbbIndex2MbbMap::iterator
- it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
- it != itEnd; ++it) {
- MachineBasicBlock* mbb = it->second;
- DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
-
- for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
- mi != miEnd; ++mi) {
- const TargetInstrDescriptor& tid =
- tm_->getInstrInfo()->get(mi->getOpcode());
- DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
- mi->print(std::cerr, tm_));
-
- // handle implicit defs
- for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
- handleRegisterDef(mbb, mi, *id);
-
- // handle explicit defs
- for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = mi->getOperand(i);
- // handle register defs - build intervals
- if (mop.isRegister() && mop.getReg() && mop.isDef())
- handleRegisterDef(mbb, mi, mop.getReg());
- }
- }
+ DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
+ DEBUG(std::cerr << "********** Function: "
+ << ((Value*)mf_->getFunction())->getName() << '\n');
+ bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
+
+ for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
+ I != E; ++I) {
+ MachineBasicBlock* mbb = I;
+ DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
+
+ MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
+ if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
+ for (; mi != miEnd; ++mi) {
+ const TargetInstrDescriptor& tid =
+ tm_->getInstrInfo()->get(mi->getOpcode());
+ DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
+
+ // handle implicit defs
+ for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
+ handleRegisterDef(mbb, mi, *id);
+
+ // handle explicit defs
+ for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand& mop = mi->getOperand(i);
+ // handle register defs - build intervals
+ if (mop.isRegister() && mop.getReg() && mop.isDef())
+ handleRegisterDef(mbb, mi, mop.getReg());
+ }
}
+ }
}
-unsigned LiveIntervals::rep(unsigned reg)
-{
- Reg2RegMap::iterator it = r2rMap_.find(reg);
- if (it != r2rMap_.end())
- return it->second = rep(it->second);
- return reg;
+/// IntA is defined as a copy from IntB and we know it only has one value
+/// number. If all of the places that IntA and IntB overlap are defined by
+/// copies from IntA to IntB, we know that these two ranges can really be
+/// merged if we adjust the value numbers. If it is safe, adjust the value
+/// numbers and return true, allowing coalescing to occur.
+bool LiveIntervals::
+AdjustIfAllOverlappingRangesAreCopiesFrom(LiveInterval &IntA,
+ LiveInterval &IntB,
+ unsigned CopyIdx) {
+ std::vector<LiveRange*> Ranges;
+ IntA.getOverlapingRanges(IntB, CopyIdx, Ranges);
+
+ assert(!Ranges.empty() && "Why didn't we do a simple join of this?");
+
+ unsigned IntBRep = rep(IntB.reg);
+
+ // Check to see if all of the overlaps (entries in Ranges) are defined by a
+ // copy from IntA. If not, exit.
+ for (unsigned i = 0, e = Ranges.size(); i != e; ++i) {
+ unsigned Idx = Ranges[i]->start;
+ MachineInstr *MI = getInstructionFromIndex(Idx);
+ unsigned SrcReg, DestReg;
+ if (!tii_->isMoveInstr(*MI, SrcReg, DestReg)) return false;
+
+ // If this copy isn't actually defining this range, it must be a live
+ // range spanning basic blocks or something.
+ if (rep(DestReg) != rep(IntA.reg)) return false;
+
+ // Check to see if this is coming from IntB. If not, bail out.
+ if (rep(SrcReg) != IntBRep) return false;
+ }
+
+ // Okay, we can change this one. Get the IntB value number that IntA is
+ // copied from.
+ unsigned ActualValNo = IntA.getLiveRangeContaining(CopyIdx-1)->ValId;
+
+ // Change all of the value numbers to the same as what we IntA is copied from.
+ for (unsigned i = 0, e = Ranges.size(); i != e; ++i)
+ Ranges[i]->ValId = ActualValNo;
+
+ return true;
}
-void LiveIntervals::joinIntervals()
-{
- DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
-
- const TargetInstrInfo& tii = *tm_->getInstrInfo();
-
- for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
- mbbi != mbbe; ++mbbi) {
- MachineBasicBlock* mbb = mbbi;
- DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
-
- for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
- mi != mie; ++mi) {
- const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
- DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
- mi->print(std::cerr, tm_););
-
- // we only join virtual registers with allocatable
- // physical registers since we do not have liveness information
- // on not allocatable physical registers
- unsigned regA, regB;
- if (tii.isMoveInstr(*mi, regA, regB) &&
- (MRegisterInfo::isVirtualRegister(regA) ||
- lv_->getAllocatablePhysicalRegisters()[regA]) &&
- (MRegisterInfo::isVirtualRegister(regB) ||
- lv_->getAllocatablePhysicalRegisters()[regB])) {
-
- // get representative registers
- regA = rep(regA);
- regB = rep(regB);
-
- // if they are already joined we continue
- if (regA == regB)
- continue;
-
- Reg2IntervalMap::iterator r2iA = r2iMap_.find(regA);
- assert(r2iA != r2iMap_.end());
- Reg2IntervalMap::iterator r2iB = r2iMap_.find(regB);
- assert(r2iB != r2iMap_.end());
-
- Intervals::iterator intA = r2iA->second;
- Intervals::iterator intB = r2iB->second;
-
- // both A and B are virtual registers
- if (MRegisterInfo::isVirtualRegister(intA->reg) &&
- MRegisterInfo::isVirtualRegister(intB->reg)) {
-
- const TargetRegisterClass *rcA, *rcB;
- rcA = mf_->getSSARegMap()->getRegClass(intA->reg);
- rcB = mf_->getSSARegMap()->getRegClass(intB->reg);
- // if they are not of the same register class we continue
- if (rcA != rcB)
- continue;
-
- // if their intervals do not overlap we join them
- if (!intB->overlaps(*intA)) {
- intA->join(*intB);
- r2iB->second = r2iA->second;
- r2rMap_.insert(std::make_pair(intB->reg, intA->reg));
- intervals_.erase(intB);
- }
- }
- else if (MRegisterInfo::isPhysicalRegister(intA->reg) ^
- MRegisterInfo::isPhysicalRegister(intB->reg)) {
- if (MRegisterInfo::isPhysicalRegister(intB->reg)) {
- std::swap(regA, regB);
- std::swap(intA, intB);
- std::swap(r2iA, r2iB);
- }
-
- assert(MRegisterInfo::isPhysicalRegister(intA->reg) &&
- MRegisterInfo::isVirtualRegister(intB->reg) &&
- "A must be physical and B must be virtual");
-
- const TargetRegisterClass *rcA, *rcB;
- rcA = mri_->getRegClass(intA->reg);
- rcB = mf_->getSSARegMap()->getRegClass(intB->reg);
- // if they are not of the same register class we continue
- if (rcA != rcB)
- continue;
-
- if (!intA->overlaps(*intB) &&
- !overlapsAliases(*intA, *intB)) {
- intA->join(*intB);
- r2iB->second = r2iA->second;
- r2rMap_.insert(std::make_pair(intB->reg, intA->reg));
- intervals_.erase(intB);
- }
- }
- }
+void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
+ DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
+
+ for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
+ mi != mie; ++mi) {
+ DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
+
+ // we only join virtual registers with allocatable
+ // physical registers since we do not have liveness information
+ // on not allocatable physical registers
+ unsigned SrcReg, DestReg;
+ if (tii_->isMoveInstr(*mi, SrcReg, DestReg) &&
+ (MRegisterInfo::isVirtualRegister(SrcReg) || allocatableRegs_[SrcReg])&&
+ (MRegisterInfo::isVirtualRegister(DestReg)||allocatableRegs_[DestReg])){
+
+ // Get representative registers.
+ SrcReg = rep(SrcReg);
+ DestReg = rep(DestReg);
+
+ // If they are already joined we continue.
+ if (SrcReg == DestReg)
+ continue;
+
+ // If they are both physical registers, we cannot join them.
+ if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
+ MRegisterInfo::isPhysicalRegister(DestReg))
+ continue;
+
+ // If they are not of the same register class, we cannot join them.
+ if (differingRegisterClasses(SrcReg, DestReg))
+ continue;
+
+ LiveInterval &SrcInt = getInterval(SrcReg);
+ LiveInterval &DestInt = getInterval(DestReg);
+ assert(SrcInt.reg == SrcReg && DestInt.reg == DestReg &&
+ "Register mapping is horribly broken!");
+
+ DEBUG(std::cerr << "\t\tInspecting " << SrcInt << " and " << DestInt
+ << ": ");
+
+ // If two intervals contain a single value and are joined by a copy, it
+ // does not matter if the intervals overlap, they can always be joined.
+ bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
+
+ unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
+
+ // If the intervals think that this is joinable, do so now.
+ if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
+ Joinable = true;
+
+ // If DestInt is actually a copy from SrcInt (which we know) that is used
+ // to define another value of SrcInt, we can change the other range of
+ // SrcInt to be the value of the range that defines DestInt, allowing a
+ // coalesce.
+ if (!Joinable && DestInt.containsOneValue() &&
+ AdjustIfAllOverlappingRangesAreCopiesFrom(SrcInt, DestInt, MIDefIdx))
+ Joinable = true;
+
+ if (!Joinable || overlapsAliases(&SrcInt, &DestInt)) {
+ DEBUG(std::cerr << "Interference!\n");
+ } else {
+ DestInt.join(SrcInt, MIDefIdx);
+ DEBUG(std::cerr << "Joined. Result = " << DestInt << "\n");
+
+ if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
+ r2iMap_.erase(SrcReg);
+ r2rMap_[SrcReg] = DestReg;
+ } else {
+ // Otherwise merge the data structures the other way so we don't lose
+ // the physreg information.
+ r2rMap_[DestReg] = SrcReg;
+ DestInt.reg = SrcReg;
+ SrcInt.swap(DestInt);
+ r2iMap_.erase(DestReg);
}
+ ++numJoins;
+ }
}
+ }
}
-bool LiveIntervals::overlapsAliases(const LiveInterval& lhs,
- const LiveInterval& rhs) const
-{
- assert(MRegisterInfo::isPhysicalRegister(lhs.reg) &&
- "first interval must describe a physical register");
-
- for (const unsigned* as = mri_->getAliasSet(lhs.reg); *as; ++as) {
- Reg2IntervalMap::const_iterator r2i = r2iMap_.find(*as);
- assert(r2i != r2iMap_.end() && "alias does not have interval?");
- if (rhs.overlaps(*r2i->second))
- return true;
- }
-
- return false;
-}
-
-LiveInterval& LiveIntervals::getOrCreateInterval(unsigned reg)
-{
- Reg2IntervalMap::iterator r2iit = r2iMap_.lower_bound(reg);
- if (r2iit == r2iMap_.end() || r2iit->first != reg) {
- intervals_.push_back(LiveInterval(reg));
- r2iit = r2iMap_.insert(r2iit, std::make_pair(reg, --intervals_.end()));
+namespace {
+ // DepthMBBCompare - Comparison predicate that sort first based on the loop
+ // depth of the basic block (the unsigned), and then on the MBB number.
+ struct DepthMBBCompare {
+ typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
+ bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
+ if (LHS.first > RHS.first) return true; // Deeper loops first
+ return LHS.first == RHS.first &&
+ LHS.second->getNumber() < RHS.second->getNumber();
}
-
- return *r2iit->second;
-}
-
-LiveInterval::LiveInterval(unsigned r)
- : reg(r),
- weight((MRegisterInfo::isPhysicalRegister(r) ? HUGE_VAL : 0.0F))
-{
-}
-
-bool LiveInterval::spilled() const
-{
- return (weight == HUGE_VAL &&
- MRegisterInfo::isVirtualRegister(reg));
+ };
}
-// An example for liveAt():
-//
-// this = [1,4), liveAt(0) will return false. The instruction defining
-// this spans slots [0,3]. The interval belongs to an spilled
-// definition of the variable it represents. This is because slot 1 is
-// used (def slot) and spans up to slot 3 (store slot).
-//
-bool LiveInterval::liveAt(unsigned index) const
-{
- Range dummy(index, index+1);
- Ranges::const_iterator r = std::upper_bound(ranges.begin(),
- ranges.end(),
- dummy);
- if (r == ranges.begin())
- return false;
-
- --r;
- return index >= r->first && index < r->second;
-}
-
-// An example for overlaps():
-//
-// 0: A = ...
-// 4: B = ...
-// 8: C = A + B ;; last use of A
-//
-// The live intervals should look like:
-//
-// A = [3, 11)
-// B = [7, x)
-// C = [11, y)
-//
-// A->overlaps(C) should return false since we want to be able to join
-// A and C.
-bool LiveInterval::overlaps(const LiveInterval& other) const
-{
- Ranges::const_iterator i = ranges.begin();
- Ranges::const_iterator ie = ranges.end();
- Ranges::const_iterator j = other.ranges.begin();
- Ranges::const_iterator je = other.ranges.end();
- if (i->first < j->first) {
- i = std::upper_bound(i, ie, *j);
- if (i != ranges.begin()) --i;
- }
- else if (j->first < i->first) {
- j = std::upper_bound(j, je, *i);
- if (j != other.ranges.begin()) --j;
- }
-
- while (i != ie && j != je) {
- if (i->first == j->first) {
- return true;
- }
- else {
- if (i->first > j->first) {
- swap(i, j);
- swap(ie, je);
- }
- assert(i->first < j->first);
-
- if (i->second > j->first) {
- return true;
- }
- else {
- ++i;
- }
- }
- }
-
- return false;
+void LiveIntervals::joinIntervals() {
+ DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
+
+ const LoopInfo &LI = getAnalysis<LoopInfo>();
+ if (LI.begin() == LI.end()) {
+ // If there are no loops in the function, join intervals in function order.
+ for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
+ I != E; ++I)
+ joinIntervalsInMachineBB(I);
+ } else {
+ // Otherwise, join intervals in inner loops before other intervals.
+ // Unfortunately we can't just iterate over loop hierarchy here because
+ // there may be more MBB's than BB's. Collect MBB's for sorting.
+ std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
+ for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
+ I != E; ++I)
+ MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
+
+ // Sort by loop depth.
+ std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
+
+ // Finally, join intervals in loop nest order.
+ for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
+ joinIntervalsInMachineBB(MBBs[i].second);
+ }
+
+ DEBUG(std::cerr << "*** Register mapping ***\n");
+ DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
+ if (r2rMap_[i])
+ std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n");
}
-void LiveInterval::addRange(unsigned start, unsigned end)
-{
- assert(start < end && "Invalid range to add!");
- DEBUG(std::cerr << " +[" << start << ',' << end << ")");
- //assert(start < end && "invalid range?");
- Range range = std::make_pair(start, end);
- Ranges::iterator it =
- ranges.insert(std::upper_bound(ranges.begin(), ranges.end(), range),
- range);
-
- it = mergeRangesForward(it);
- it = mergeRangesBackward(it);
+/// Return true if the two specified registers belong to different register
+/// classes. The registers may be either phys or virt regs.
+bool LiveIntervals::differingRegisterClasses(unsigned RegA,
+ unsigned RegB) const {
+
+ // Get the register classes for the first reg.
+ if (MRegisterInfo::isPhysicalRegister(RegA)) {
+ assert(MRegisterInfo::isVirtualRegister(RegB) &&
+ "Shouldn't consider two physregs!");
+ return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
+ }
+
+ // Compare against the regclass for the second reg.
+ const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
+ if (MRegisterInfo::isVirtualRegister(RegB))
+ return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
+ else
+ return !RegClass->contains(RegB);
}
-void LiveInterval::join(const LiveInterval& other)
-{
- DEBUG(std::cerr << "\t\tjoining " << *this << " with " << other << '\n');
- Ranges::iterator cur = ranges.begin();
-
- for (Ranges::const_iterator i = other.ranges.begin(),
- e = other.ranges.end(); i != e; ++i) {
- cur = ranges.insert(std::upper_bound(cur, ranges.end(), *i), *i);
- cur = mergeRangesForward(cur);
- cur = mergeRangesBackward(cur);
- }
- weight += other.weight;
- ++numJoins;
-}
+bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
+ const LiveInterval *RHS) const {
+ if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
+ if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
+ return false; // vreg-vreg merge has no aliases!
+ std::swap(LHS, RHS);
+ }
-LiveInterval::Ranges::iterator LiveInterval::
-mergeRangesForward(Ranges::iterator it)
-{
- Ranges::iterator n;
- while ((n = next(it)) != ranges.end()) {
- if (n->first > it->second)
- break;
- it->second = std::max(it->second, n->second);
- n = ranges.erase(n);
- }
- return it;
-}
+ assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
+ MRegisterInfo::isVirtualRegister(RHS->reg) &&
+ "first interval must describe a physical register");
-LiveInterval::Ranges::iterator LiveInterval::
-mergeRangesBackward(Ranges::iterator it)
-{
- while (it != ranges.begin()) {
- Ranges::iterator p = prior(it);
- if (it->first > p->second)
- break;
-
- it->first = std::min(it->first, p->first);
- it->second = std::max(it->second, p->second);
- it = ranges.erase(p);
- }
+ for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
+ if (RHS->overlaps(getInterval(*AS)))
+ return true;
- return it;
+ return false;
}
-std::ostream& llvm::operator<<(std::ostream& os, const LiveInterval& li)
-{
- os << "%reg" << li.reg << ',' << li.weight;
- if (li.empty())
- return os << "EMPTY";
-
- os << " = ";
- for (LiveInterval::Ranges::const_iterator
- i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
- os << "[" << i->first << "," << i->second << ")";
- }
- return os;
+LiveInterval LiveIntervals::createInterval(unsigned reg) {
+ float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
+ (float)HUGE_VAL :0.0F;
+ return LiveInterval(reg, Weight);
}
projects / oota-llvm.git / blobdiff