Add coalescing to register allocator. A hint is added to each interval

[oota-llvm.git] / lib / CodeGen / LiveIntervalAnalysis.cpp

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index b34a65bc6443577dbd6b3b614ae86e52de804cde..4d0916046a0f4d45989d2913e19f8bd2856601b7 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -108,6 +108,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
 
     // compute spill weights
     const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
+    const TargetInstrInfo& tii = tm_->getInstrInfo();
 
     for (MbbIndex2MbbMap::iterator
              it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
@@ -130,6 +131,21 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
                 assert(r2iit != r2iMap_.end());
                 intervals_[r2iit->second].weight += pow(10.0F, loopDepth);
             }
+
+            // add hints for coalescing
+            unsigned src, dst;
+            if (tii.isMoveInstr(*instr, src, dst)) {
+                if (src >= MRegisterInfo::FirstVirtualRegister) {
+                    Reg2IntervalMap::iterator r2iit = r2iMap_.find(src);
+                    assert(r2iit != r2iMap_.end());
+                    intervals_[r2iit->second].hint = dst;
+                }
+                if (dst >= MRegisterInfo::FirstVirtualRegister) {
+                    Reg2IntervalMap::iterator r2iit = r2iMap_.find(dst);
+                    assert(r2iit != r2iMap_.end());
+                    intervals_[r2iit->second].hint = src;
+                }
+            }
         }
     }
 
@@ -329,7 +345,7 @@ void LiveIntervals::computeIntervals()
 }
 
 LiveIntervals::Interval::Interval(unsigned r)
-    : reg(r),
+    : reg(r), hint(0),
       weight((r < MRegisterInfo::FirstVirtualRegister ?
               std::numeric_limits<float>::max() : 0.0F))
 {