#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "VirtRegMap.h"
#include "llvm/Value.h"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
static cl::opt<int> SplitLimit("split-limit",
cl::init(-1), cl::Hidden);
+static cl::opt<bool> EnableAggressiveRemat("aggressive-remat", cl::Hidden);
+
+static cl::opt<bool> EnableFastSpilling("fast-spill",
+ cl::init(false), cl::Hidden);
+
STATISTIC(numIntervals, "Number of original intervals");
-STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
STATISTIC(numFolds , "Number of loads/stores folded into instructions");
STATISTIC(numSplits , "Number of intervals split");
static RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<AliasAnalysis>();
+ AU.addPreserved<AliasAnalysis>();
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
- AU.addPreservedID(PHIEliminationID);
- AU.addRequiredID(PHIEliminationID);
+
+ if (!StrongPHIElim) {
+ AU.addPreservedID(PHIEliminationID);
+ AU.addRequiredID(PHIEliminationID);
+ }
+
AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU);
}
void LiveIntervals::releaseMemory() {
+ // Free the live intervals themselves.
+ for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
+ E = r2iMap_.end(); I != E; ++I)
+ delete I->second;
+
MBB2IdxMap.clear();
Idx2MBBMap.clear();
mi2iMap_.clear();
r2iMap_.clear();
// Release VNInfo memroy regions after all VNInfo objects are dtor'd.
VNInfoAllocator.Reset();
- for (unsigned i = 0, e = ClonedMIs.size(); i != e; ++i)
- delete ClonedMIs[i];
+ while (!ClonedMIs.empty()) {
+ MachineInstr *MI = ClonedMIs.back();
+ ClonedMIs.pop_back();
+ mf_->DeleteMachineInstr(MI);
+ }
}
void LiveIntervals::computeNumbering() {
Index2MiMap OldI2MI = i2miMap_;
+ std::vector<IdxMBBPair> OldI2MBB = Idx2MBBMap;
Idx2MBBMap.clear();
MBB2IdxMap.clear();
mi2iMap_.clear();
i2miMap_.clear();
+ FunctionSize = 0;
+
// Number MachineInstrs and MachineBasicBlocks.
// Initialize MBB indexes to a sentinal.
MBB2IdxMap.resize(mf_->getNumBlockIDs(), std::make_pair(~0U,~0U));
MBB != E; ++MBB) {
unsigned StartIdx = MIIndex;
+ // Insert an empty slot at the beginning of each block.
+ MIIndex += InstrSlots::NUM;
+ i2miMap_.push_back(0);
+
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
+ inserted = true;
i2miMap_.push_back(I);
MIIndex += InstrSlots::NUM;
+ FunctionSize++;
+
+ // Insert max(1, numdefs) empty slots after every instruction.
+ unsigned Slots = I->getDesc().getNumDefs();
+ if (Slots == 0)
+ Slots = 1;
+ MIIndex += InstrSlots::NUM * Slots;
+ while (Slots--)
+ i2miMap_.push_back(0);
}
-
+
// Set the MBB2IdxMap entry for this MBB.
- MBB2IdxMap[MBB->getNumber()] = (StartIdx == MIIndex)
- ? std::make_pair(StartIdx, StartIdx) // Empty MBB
- : std::make_pair(StartIdx, MIIndex - 1);
+ MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
}
std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
if (!OldI2MI.empty())
- for (iterator I = begin(), E = end(); I != E; ++I)
- for (LiveInterval::iterator LI = I->second.begin(), LE = I->second.end();
- LI != LE; ++LI) {
+ for (iterator OI = begin(), OE = end(); OI != OE; ++OI) {
+ for (LiveInterval::iterator LI = OI->second->begin(),
+ LE = OI->second->end(); LI != LE; ++LI) {
// Remap the start index of the live range to the corresponding new
// number, or our best guess at what it _should_ correspond to if the
// original instruction has been erased. This is either the following
// instruction or its predecessor.
+ unsigned index = LI->start / InstrSlots::NUM;
unsigned offset = LI->start % InstrSlots::NUM;
- if (OldI2MI[LI->start / InstrSlots::NUM])
- LI->start = mi2iMap_[OldI2MI[LI->start / InstrSlots::NUM]] + offset;
- else {
- unsigned i = 0;
- MachineInstr* newInstr = 0;
- do {
- newInstr = OldI2MI[LI->start / InstrSlots::NUM + i];
- i++;
- } while (!newInstr);
+ if (offset == InstrSlots::LOAD) {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->start);
+ // Take the pair containing the index
+ std::vector<IdxMBBPair>::const_iterator J =
+ (I == OldI2MBB.end() && OldI2MBB.size()>0) ? (I-1): I;
- if (mi2iMap_[newInstr] ==
- MBB2IdxMap[newInstr->getParent()->getNumber()].first)
- LI->start = mi2iMap_[newInstr];
- else
- LI->start = mi2iMap_[newInstr] - InstrSlots::NUM + offset;
+ LI->start = getMBBStartIdx(J->second);
+ } else {
+ LI->start = mi2iMap_[OldI2MI[index]] + offset;
}
// Remap the ending index in the same way that we remapped the start,
// except for the final step where we always map to the immediately
// following instruction.
- if (LI->end / InstrSlots::NUM < OldI2MI.size()) {
- offset = LI->end % InstrSlots::NUM;
- if (OldI2MI[LI->end / InstrSlots::NUM])
- LI->end = mi2iMap_[OldI2MI[LI->end / InstrSlots::NUM]] + offset;
- else {
- unsigned i = 0;
- MachineInstr* newInstr = 0;
- do {
- newInstr = OldI2MI[LI->end / InstrSlots::NUM + i];
- i++;
- } while (!newInstr);
-
- LI->end = mi2iMap_[newInstr];
- }
+ index = (LI->end - 1) / InstrSlots::NUM;
+ offset = LI->end % InstrSlots::NUM;
+ if (offset == InstrSlots::LOAD) {
+ // VReg dies at end of block.
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
+ --I;
+
+ LI->end = getMBBEndIdx(I->second) + 1;
} else {
- LI->end = i2miMap_.size() * InstrSlots::NUM;
+ unsigned idx = index;
+ while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
+
+ if (index != OldI2MI.size())
+ LI->end = mi2iMap_[OldI2MI[index]] + (idx == index ? offset : 0);
+ else
+ LI->end = InstrSlots::NUM * i2miMap_.size();
}
+ }
+
+ for (LiveInterval::vni_iterator VNI = OI->second->vni_begin(),
+ VNE = OI->second->vni_end(); VNI != VNE; ++VNI) {
+ VNInfo* vni = *VNI;
// Remap the VNInfo def index, which works the same as the
- // start indices above.
- VNInfo* vni = LI->valno;
- offset = vni->def % InstrSlots::NUM;
- if (OldI2MI[vni->def / InstrSlots::NUM])
- vni->def = mi2iMap_[OldI2MI[vni->def / InstrSlots::NUM]] + offset;
- else {
- unsigned i = 0;
- MachineInstr* newInstr = 0;
- do {
- newInstr = OldI2MI[vni->def / InstrSlots::NUM + i];
- i++;
- } while (!newInstr);
+ // start indices above. VN's with special sentinel defs
+ // don't need to be remapped.
+ if (vni->def != ~0U && vni->def != ~1U) {
+ unsigned index = vni->def / InstrSlots::NUM;
+ unsigned offset = vni->def % InstrSlots::NUM;
+ if (offset == InstrSlots::LOAD) {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->def);
+ // Take the pair containing the index
+ std::vector<IdxMBBPair>::const_iterator J =
+ (I == OldI2MBB.end() && OldI2MBB.size()>0) ? (I-1): I;
- if (mi2iMap_[newInstr] ==
- MBB2IdxMap[newInstr->getParent()->getNumber()].first)
- vni->def = mi2iMap_[newInstr];
- else
- vni->def = mi2iMap_[newInstr] - InstrSlots::NUM + offset;
+ vni->def = getMBBStartIdx(J->second);
+ } else {
+ vni->def = mi2iMap_[OldI2MI[index]] + offset;
+ }
}
// Remap the VNInfo kill indices, which works the same as
// the end indices above.
for (size_t i = 0; i < vni->kills.size(); ++i) {
- offset = vni->kills[i] % InstrSlots::NUM;
- if (OldI2MI[vni->kills[i] / InstrSlots::NUM])
- vni->kills[i] = mi2iMap_[OldI2MI[vni->kills[i] / InstrSlots::NUM]] +
- offset;
- else {
- unsigned e = 0;
- MachineInstr* newInstr = 0;
- do {
- newInstr = OldI2MI[vni->kills[i] / InstrSlots::NUM + e];
- e++;
- } while (!newInstr);
+ // PHI kills don't need to be remapped.
+ if (!vni->kills[i]) continue;
+
+ unsigned index = (vni->kills[i]-1) / InstrSlots::NUM;
+ unsigned offset = vni->kills[i] % InstrSlots::NUM;
+ if (offset == InstrSlots::LOAD) {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
+ --I;
+
+ vni->kills[i] = getMBBEndIdx(I->second);
+ } else {
+ unsigned idx = index;
+ while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
- vni->kills[i] = mi2iMap_[newInstr];
+ if (index != OldI2MI.size())
+ vni->kills[i] = mi2iMap_[OldI2MI[index]] +
+ (idx == index ? offset : 0);
+ else
+ vni->kills[i] = InstrSlots::NUM * i2miMap_.size();
}
}
}
+ }
}
/// runOnMachineFunction - Register allocate the whole function
tm_ = &fn.getTarget();
tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
+ aa_ = &getAnalysis<AliasAnalysis>();
lv_ = &getAnalysis<LiveVariables>();
allocatableRegs_ = tri_->getAllocatableSet(fn);
numIntervals += getNumIntervals();
- DOUT << "********** INTERVALS **********\n";
- for (iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(DOUT, tri_);
- DOUT << "\n";
- }
-
- numIntervalsAfter += getNumIntervals();
DEBUG(dump());
return true;
}
void LiveIntervals::print(std::ostream &O, const Module* ) const {
O << "********** INTERVALS **********\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(O, tri_);
+ I->second->print(O, tri_);
O << "\n";
}
continue;
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
- if (!mop.isRegister())
+ if (!mop.isReg())
continue;
unsigned PhysReg = mop.getReg();
if (PhysReg == 0 || PhysReg == li.reg)
return false;
}
+/// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except
+/// it can check use as well.
+bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li,
+ unsigned Reg, bool CheckUse,
+ SmallPtrSet<MachineInstr*,32> &JoinedCopies) {
+ for (LiveInterval::Ranges::const_iterator
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ for (unsigned index = getBaseIndex(I->start),
+ end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
+ index += InstrSlots::NUM) {
+ // Skip deleted instructions.
+ MachineInstr *MI = 0;
+ while (index != end) {
+ MI = getInstructionFromIndex(index);
+ if (MI)
+ break;
+ index += InstrSlots::NUM;
+ }
+ if (index == end) break;
+
+ if (JoinedCopies.count(MI))
+ continue;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (!MO.isReg())
+ continue;
+ if (MO.isUse() && !CheckUse)
+ continue;
+ unsigned PhysReg = MO.getReg();
+ if (PhysReg == 0 || TargetRegisterInfo::isVirtualRegister(PhysReg))
+ continue;
+ if (tri_->isSubRegister(Reg, PhysReg))
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+
void LiveIntervals::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
cerr << tri_->getName(reg);
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
- unsigned MIIdx,
+ unsigned MIIdx, MachineOperand& MO,
+ unsigned MOIdx,
LiveInterval &interval) {
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (interval.empty()) {
// Get the Idx of the defining instructions.
unsigned defIndex = getDefIndex(MIIdx);
+ // Earlyclobbers move back one.
+ if (MO.isEarlyClobber())
+ defIndex = getUseIndex(MIIdx);
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg;
mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
tii_->isMoveInstr(*mi, SrcReg, DstReg))
CopyMI = mi;
+ // Earlyclobbers move back one.
ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
assert(ValNo->id == 0 && "First value in interval is not 0?");
// of the defining block, potentially live across some blocks, then is
// live into some number of blocks, but gets killed. Start by adding a
// range that goes from this definition to the end of the defining block.
- LiveRange NewLR(defIndex,
- getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
- ValNo);
+ LiveRange NewLR(defIndex, getMBBEndIdx(mbb)+1, ValNo);
DOUT << " +" << NewLR;
interval.addRange(NewLR);
// Iterate over all of the blocks that the variable is completely
// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
// live interval.
- for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
- if (vi.AliveBlocks[i]) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
- if (!MBB->empty()) {
- LiveRange LR(getMBBStartIdx(i),
- getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
- ValNo);
- interval.addRange(LR);
- DOUT << " +" << LR;
- }
- }
+ for (int i = vi.AliveBlocks.find_first(); i != -1;
+ i = vi.AliveBlocks.find_next(i)) {
+ LiveRange LR(getMBBStartIdx(i),
+ getMBBEndIdx(i)+1, // MBB ends at -1.
+ ValNo);
+ interval.addRange(LR);
+ DOUT << " +" << LR;
}
// Finally, this virtual register is live from the start of any killing
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(interval.reg)) {
+ if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
assert(interval.containsOneValue());
unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
unsigned RedefIndex = getDefIndex(MIIdx);
+ // It cannot be an early clobber MO.
+ assert(!MO.isEarlyClobber() && "Unexpected early clobber!");
const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
VNInfo *OldValNo = OldLR->valno;
// If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot.
- if (mi->registerDefIsDead(interval.reg, tri_))
+ if (MO.isDead())
interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
DOUT << " RESULT: ";
// live until the end of the block. We've already taken care of the
// rest of the live range.
unsigned defIndex = getDefIndex(MIIdx);
+ // It cannot be an early clobber MO.
+ assert(!MO.isEarlyClobber() && "Unexpected early clobber!");
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
- unsigned killIndex = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
+ unsigned killIndex = getMBBEndIdx(mbb) + 1;
LiveRange LR(defIndex, killIndex, ValNo);
interval.addRange(LR);
interval.addKill(ValNo, killIndex);
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
unsigned MIIdx,
+ MachineOperand& MO,
LiveInterval &interval,
MachineInstr *CopyMI) {
// A physical register cannot be live across basic block, so its
unsigned baseIndex = MIIdx;
unsigned start = getDefIndex(baseIndex);
+ // Earlyclobbers move back one.
+ if (MO.isEarlyClobber())
+ start = getUseIndex(MIIdx);
unsigned end = start;
// If it is not used after definition, it is considered dead at
// the instruction defining it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
- if (mi->registerDefIsDead(interval.reg, tri_)) {
+ if (MO.isDead()) {
DOUT << " dead";
- end = getDefIndex(start) + 1;
+ end = start + 1;
goto exit;
}
// If it is not dead on definition, it must be killed by a
// subsequent instruction. Hence its interval is:
// [defSlot(def), useSlot(kill)+1)
+ baseIndex += InstrSlots::NUM;
while (++mi != MBB->end()) {
- baseIndex += InstrSlots::NUM;
+ while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(baseIndex) == 0)
+ baseIndex += InstrSlots::NUM;
if (mi->killsRegister(interval.reg, tri_)) {
DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
// it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
DOUT << " dead";
- end = getDefIndex(start) + 1;
+ end = start + 1;
goto exit;
}
+
+ baseIndex += InstrSlots::NUM;
}
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
// and never used.
assert(!CopyMI && "physreg was not killed in defining block!");
- end = getDefIndex(start) + 1; // It's dead.
+ end = start + 1;
exit:
assert(start < end && "did not find end of interval?");
// Already exists? Extend old live interval.
LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
- VNInfo *ValNo = (OldLR != interval.end())
+ bool Extend = OldLR != interval.end();
+ VNInfo *ValNo = Extend
? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
+ if (MO.isEarlyClobber() && Extend)
+ ValNo->redefByEC = true;
LiveRange LR(start, end, ValNo);
interval.addRange(LR);
interval.addKill(LR.valno, end);
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
unsigned MIIdx,
- unsigned reg) {
- if (TargetRegisterInfo::isVirtualRegister(reg))
- handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
- else if (allocatableRegs_[reg]) {
+ MachineOperand& MO,
+ unsigned MOIdx) {
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
+ getOrCreateInterval(MO.getReg()));
+ else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
tii_->isMoveInstr(*MI, SrcReg, DstReg))
CopyMI = MI;
- handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI);
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ getOrCreateInterval(MO.getReg()), CopyMI);
// Def of a register also defines its sub-registers.
- for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
+ for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS)
// If MI also modifies the sub-register explicitly, avoid processing it
// more than once. Do not pass in TRI here so it checks for exact match.
if (!MI->modifiesRegister(*AS))
- handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ getOrCreateInterval(*AS), 0);
}
}
MachineBasicBlock::iterator mi = MBB->begin();
unsigned baseIndex = MIIdx;
unsigned start = baseIndex;
- unsigned end = start;
+ while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(baseIndex) == 0)
+ baseIndex += InstrSlots::NUM;
+ unsigned end = baseIndex;
+
while (mi != MBB->end()) {
if (mi->killsRegister(interval.reg, tri_)) {
DOUT << " killed";
}
baseIndex += InstrSlots::NUM;
+ while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(baseIndex) == 0)
+ baseIndex += InstrSlots::NUM;
++mi;
}
}
}
- LiveRange LR(start, end, interval.getNextValue(start, 0, VNInfoAllocator));
+ LiveRange LR(start, end, interval.getNextValue(~0U, 0, VNInfoAllocator));
interval.addRange(LR);
interval.addKill(LR.valno, end);
DOUT << " +" << LR << '\n';
/// registers. for some ordering of the machine instructions [1,N] a
/// live interval is an interval [i, j) where 1 <= i <= j < N for
/// which a variable is live
-void LiveIntervals::computeIntervals() {
+void LiveIntervals::computeIntervals() {
+
DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
<< "********** Function: "
<< ((Value*)mf_->getFunction())->getName() << '\n';
- // Track the index of the current machine instr.
- unsigned MIIndex = 0;
+
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
+ // Track the index of the current machine instr.
+ unsigned MIIndex = getMBBStartIdx(MBB);
DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
true);
}
+ // Skip over empty initial indices.
+ while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(MIIndex) == 0)
+ MIIndex += InstrSlots::NUM;
+
for (; MI != miEnd; ++MI) {
DOUT << MIIndex << "\t" << *MI;
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
- if (MO.isRegister() && MO.getReg() && MO.isDef())
- handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
+ if (MO.isReg() && MO.getReg() && MO.isDef()) {
+ handleRegisterDef(MBB, MI, MIIndex, MO, i);
+ }
}
+
+ // Skip over the empty slots after each instruction.
+ unsigned Slots = MI->getDesc().getNumDefs();
+ if (Slots == 0)
+ Slots = 1;
+ MIIndex += InstrSlots::NUM * Slots;
- MIIndex += InstrSlots::NUM;
+ // Skip over empty indices.
+ while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
+ getInstructionFromIndex(MIIndex) == 0)
+ MIIndex += InstrSlots::NUM;
}
}
}
-bool LiveIntervals::findLiveInMBBs(const LiveRange &LR,
+bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), LR.start);
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
bool ResVal = false;
while (I != Idx2MBBMap.end()) {
- if (LR.end <= I->first)
+ if (I->first >= End)
break;
MBBs.push_back(I->second);
ResVal = true;
return ResVal;
}
+bool LiveIntervals::findReachableMBBs(unsigned Start, unsigned End,
+ SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
-LiveInterval LiveIntervals::createInterval(unsigned reg) {
+ bool ResVal = false;
+ while (I != Idx2MBBMap.end()) {
+ if (I->first > End)
+ break;
+ MachineBasicBlock *MBB = I->second;
+ if (getMBBEndIdx(MBB) > End)
+ break;
+ for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
+ SE = MBB->succ_end(); SI != SE; ++SI)
+ MBBs.push_back(*SI);
+ ResVal = true;
+ ++I;
+ }
+ return ResVal;
+}
+
+LiveInterval* LiveIntervals::createInterval(unsigned reg) {
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
HUGE_VALF : 0.0F;
- return LiveInterval(reg, Weight);
+ return new LiveInterval(reg, Weight);
}
/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
if (!VNI->copy)
return 0;
- if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
- return VNI->copy->getOperand(1).getReg();
- if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
+ if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
+ // If it's extracting out of a physical register, return the sub-register.
+ unsigned Reg = VNI->copy->getOperand(1).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
+ Reg = tri_->getSubReg(Reg, VNI->copy->getOperand(2).getImm());
+ return Reg;
+ } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
return VNI->copy->getOperand(2).getReg();
+
unsigned SrcReg, DstReg;
if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg))
return SrcReg;
unsigned RegOp = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || Reg == li.reg)
assert(!RegOp &&
"Can't rematerialize instruction with multiple register operand!");
RegOp = MO.getReg();
+#ifndef NDEBUG
break;
+#endif
}
return RegOp;
}
/// val# of the specified interval is re-materializable.
bool LiveIntervals::isReMaterializable(const LiveInterval &li,
const VNInfo *ValNo, MachineInstr *MI,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
bool &isLoad) {
if (DisableReMat)
return false;
- isLoad = false;
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return true;
// This is a load from fixed stack slot. It can be rematerialized.
return true;
- if (tii_->isTriviallyReMaterializable(MI)) {
+ // If the target-specific rules don't identify an instruction as
+ // being trivially rematerializable, use some target-independent
+ // rules.
+ if (!MI->getDesc().isRematerializable() ||
+ !tii_->isTriviallyReMaterializable(MI)) {
+ if (!EnableAggressiveRemat)
+ return false;
+
+ // If the instruction accesses memory but the memoperands have been lost,
+ // we can't analyze it.
const TargetInstrDesc &TID = MI->getDesc();
- isLoad = TID.isSimpleLoad();
-
- unsigned ImpUse = getReMatImplicitUse(li, MI);
- if (ImpUse) {
- const LiveInterval &ImpLi = getInterval(ImpUse);
- for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
- re = mri_->use_end(); ri != re; ++ri) {
- MachineInstr *UseMI = &*ri;
- unsigned UseIdx = getInstructionIndex(UseMI);
- if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
+ if ((TID.mayLoad() || TID.mayStore()) && MI->memoperands_empty())
+ return false;
+
+ // Avoid instructions obviously unsafe for remat.
+ if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable())
+ return false;
+
+ // If the instruction accesses memory and the memory could be non-constant,
+ // assume the instruction is not rematerializable.
+ for (std::list<MachineMemOperand>::const_iterator
+ I = MI->memoperands_begin(), E = MI->memoperands_end(); I != E; ++I){
+ const MachineMemOperand &MMO = *I;
+ if (MMO.isVolatile() || MMO.isStore())
+ return false;
+ const Value *V = MMO.getValue();
+ if (!V)
+ return false;
+ if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
+ if (!PSV->isConstant(mf_->getFrameInfo()))
+ return false;
+ } else if (!aa_->pointsToConstantMemory(V))
+ return false;
+ }
+
+ // If any of the registers accessed are non-constant, conservatively assume
+ // the instruction is not rematerializable.
+ unsigned ImpUse = 0;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg()) {
+ unsigned Reg = MO.getReg();
+ if (Reg == 0)
continue;
- if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
+ return false;
+
+ // Only allow one def, and that in the first operand.
+ if (MO.isDef() != (i == 0))
return false;
+
+ // Only allow constant-valued registers.
+ bool IsLiveIn = mri_->isLiveIn(Reg);
+ MachineRegisterInfo::def_iterator I = mri_->def_begin(Reg),
+ E = mri_->def_end();
+
+ // For the def, it should be the only def of that register.
+ if (MO.isDef() && (next(I) != E || IsLiveIn))
+ return false;
+
+ if (MO.isUse()) {
+ // Only allow one use other register use, as that's all the
+ // remat mechanisms support currently.
+ if (Reg != li.reg) {
+ if (ImpUse == 0)
+ ImpUse = Reg;
+ else if (Reg != ImpUse)
+ return false;
+ }
+ // For the use, there should be only one associated def.
+ if (I != E && (next(I) != E || IsLiveIn))
+ return false;
+ }
}
}
- return true;
}
- return false;
+ unsigned ImpUse = getReMatImplicitUse(li, MI);
+ if (ImpUse) {
+ const LiveInterval &ImpLi = getInterval(ImpUse);
+ for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
+ re = mri_->use_end(); ri != re; ++ri) {
+ MachineInstr *UseMI = &*ri;
+ unsigned UseIdx = getInstructionIndex(UseMI);
+ if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
+ continue;
+ if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
+ return false;
+ }
+
+ // If a register operand of the re-materialized instruction is going to
+ // be spilled next, then it's not legal to re-materialize this instruction.
+ for (unsigned i = 0, e = SpillIs.size(); i != e; ++i)
+ if (ImpUse == SpillIs[i]->reg)
+ return false;
+ }
+ return true;
+}
+
+/// isReMaterializable - Returns true if the definition MI of the specified
+/// val# of the specified interval is re-materializable.
+bool LiveIntervals::isReMaterializable(const LiveInterval &li,
+ const VNInfo *ValNo, MachineInstr *MI) {
+ SmallVector<LiveInterval*, 4> Dummy1;
+ bool Dummy2;
+ return isReMaterializable(li, ValNo, MI, Dummy1, Dummy2);
}
/// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable.
-bool LiveIntervals::isReMaterializable(const LiveInterval &li, bool &isLoad) {
+bool LiveIntervals::isReMaterializable(const LiveInterval &li,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ bool &isLoad) {
isLoad = false;
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
i != e; ++i) {
MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx);
bool DefIsLoad = false;
if (!ReMatDefMI ||
- !isReMaterializable(li, VNI, ReMatDefMI, DefIsLoad))
+ !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
return false;
isLoad |= DefIsLoad;
}
// Attempt to fold the memory reference into the instruction. If
// we can do this, we don't need to insert spill code.
- if (lv_)
- lv_->instructionChanged(MI, fmi);
- else
- fmi->copyKillDeadInfo(MI, tri_);
MachineBasicBlock &MBB = *MI->getParent();
if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
// use operand. Make sure we rewrite that as well.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister())
+ if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
SmallVector<int, 4> &ReMatIds,
const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
- std::map<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs) {
+ DenseMap<unsigned,unsigned> &MBBVRegsMap,
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
+ MachineBasicBlock *MBB = MI->getParent();
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
bool CanFold = false;
RestartInstruction:
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
- if (!mop.isRegister())
+ if (!mop.isReg())
continue;
unsigned Reg = mop.getReg();
unsigned RegI = Reg;
Ops.push_back(i);
for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
const MachineOperand &MOj = MI->getOperand(j);
- if (!MOj.isRegister())
+ if (!MOj.isReg())
continue;
unsigned RegJ = MOj.getReg();
if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
}
}
- if (TryFold) {
+ if (HasUse && !li.liveAt(getUseIndex(index)))
+ // Must be defined by an implicit def. It should not be spilled. Note,
+ // this is for correctness reason. e.g.
+ // 8 %reg1024<def> = IMPLICIT_DEF
+ // 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
+ // The live range [12, 14) are not part of the r1024 live interval since
+ // it's defined by an implicit def. It will not conflicts with live
+ // interval of r1025. Now suppose both registers are spilled, you can
+ // easily see a situation where both registers are reloaded before
+ // the INSERT_SUBREG and both target registers that would overlap.
+ HasUse = false;
+
+ // Update stack slot spill weight if we are splitting.
+ float Weight = getSpillWeight(HasDef, HasUse, loopDepth);
+ if (!TrySplit)
+ SSWeight += Weight;
+
+ // Create a new virtual register for the spill interval.
+ // Create the new register now so we can map the fold instruction
+ // to the new register so when it is unfolded we get the correct
+ // answer.
+ bool CreatedNewVReg = false;
+ if (NewVReg == 0) {
+ NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ CreatedNewVReg = true;
+ }
+
+ if (!TryFold)
+ CanFold = false;
+ else {
// Do not fold load / store here if we are splitting. We'll find an
// optimal point to insert a load / store later.
if (!TrySplit) {
if (tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
- Ops, FoldSS, FoldSlot, Reg)) {
+ Ops, FoldSS, FoldSlot, NewVReg)) {
// Folding the load/store can completely change the instruction in
// unpredictable ways, rescan it from the beginning.
+
+ if (FoldSS) {
+ // We need to give the new vreg the same stack slot as the
+ // spilled interval.
+ vrm.assignVirt2StackSlot(NewVReg, FoldSlot);
+ }
+
HasUse = false;
HasDef = false;
CanFold = false;
- if (isRemoved(MI))
+ if (isRemoved(MI)) {
+ SSWeight -= Weight;
break;
+ }
goto RestartInstruction;
}
} else {
+ // We'll try to fold it later if it's profitable.
CanFold = canFoldMemoryOperand(MI, Ops, DefIsReMat);
}
- } else
- CanFold = false;
-
- // Create a new virtual register for the spill interval.
- bool CreatedNewVReg = false;
- if (NewVReg == 0) {
- NewVReg = mri_->createVirtualRegister(rc);
- vrm.grow();
- CreatedNewVReg = true;
}
+
mop.setReg(NewVReg);
if (mop.isImplicit())
rewriteImplicitOps(li, MI, NewVReg, vrm);
SmallVector<int, 4> &ReMatIds,
const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
- std::map<unsigned, std::vector<SRInfo> > &SpillIdxes,
+ DenseMap<unsigned, std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
- std::map<unsigned, std::vector<SRInfo> > &RestoreIdxes,
- std::map<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs) {
+ DenseMap<unsigned, std::vector<SRInfo> > &RestoreIdxes,
+ DenseMap<unsigned,unsigned> &MBBVRegsMap,
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
bool AllCanFold = true;
unsigned NewVReg = 0;
unsigned start = getBaseIndex(I->start);
unsigned index = getInstructionIndex(MI);
if (index < start || index >= end)
continue;
+ if (O.isUse() && !li.liveAt(getUseIndex(index)))
+ // Must be defined by an implicit def. It should not be spilled. Note,
+ // this is for correctness reason. e.g.
+ // 8 %reg1024<def> = IMPLICIT_DEF
+ // 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
+ // The live range [12, 14) are not part of the r1024 live interval since
+ // it's defined by an implicit def. It will not conflicts with live
+ // interval of r1025. Now suppose both registers are spilled, you can
+ // easily see a situation where both registers are reloaded before
+ // the INSERT_SUBREG and both target registers that would overlap.
+ continue;
RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));
}
std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare());
unsigned MBBId = MBB->getNumber();
unsigned ThisVReg = 0;
if (TrySplit) {
- std::map<unsigned,unsigned>::const_iterator NVI = MBBVRegsMap.find(MBBId);
+ DenseMap<unsigned,unsigned>::iterator NVI = MBBVRegsMap.find(MBBId);
if (NVI != MBBVRegsMap.end()) {
ThisVReg = NVI->second;
// One common case:
bool HasDef = false;
bool HasUse = false;
bool CanFold = rewriteInstructionForSpills(li, I->valno, TrySplit,
- index, end, MI, ReMatOrigDefMI, ReMatDefMI,
- Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
- CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
- ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs);
+ index, end, MI, ReMatOrigDefMI, ReMatDefMI,
+ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
+ CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
+ ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight);
if (!HasDef && !HasUse)
continue;
if (VNI)
HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index));
}
- std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator SII =
SpillIdxes.find(MBBId);
if (!HasKill) {
if (SII == SpillIdxes.end()) {
}
if (HasUse) {
- std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator SII =
SpillIdxes.find(MBBId);
if (SII != SpillIdxes.end() &&
SII->second.back().vreg == NewVReg &&
(int)index > SII->second.back().index)
// Use(s) following the last def, it's not safe to fold the spill.
SII->second.back().canFold = false;
- std::map<unsigned, std::vector<SRInfo> >::iterator RII =
+ DenseMap<unsigned, std::vector<SRInfo> >::iterator RII =
RestoreIdxes.find(MBBId);
if (RII != RestoreIdxes.end() && RII->second.back().vreg == NewVReg)
// If we are splitting live intervals, only fold if it's the first
bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
- std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return false;
std::vector<SRInfo> &Restores = RestoreIdxes[Id];
void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
- std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return;
std::vector<SRInfo> &Restores = RestoreIdxes[Id];
}
}
+namespace {
+ struct LISorter {
+ bool operator()(LiveInterval* A, LiveInterval* B) {
+ return A->beginNumber() < B->beginNumber();
+ }
+ };
+}
std::vector<LiveInterval*> LiveIntervals::
-addIntervalsForSpills(const LiveInterval &li,
- const MachineLoopInfo *loopInfo, VirtRegMap &vrm) {
- // Since this is called after the analysis is done we don't know if
- // LiveVariables is available
- lv_ = getAnalysisToUpdate<LiveVariables>();
+addIntervalsForSpillsFast(const LiveInterval &li,
+ const MachineLoopInfo *loopInfo,
+ VirtRegMap &vrm, float& SSWeight) {
+ unsigned slot = vrm.assignVirt2StackSlot(li.reg);
+
+ std::vector<LiveInterval*> added;
+ assert(li.weight != HUGE_VALF &&
+ "attempt to spill already spilled interval!");
+
+ DOUT << "\t\t\t\tadding intervals for spills for interval: ";
+ DEBUG(li.dump());
+ DOUT << '\n';
+
+ const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
+
+ SSWeight = 0.0f;
+
+ MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg);
+ while (RI != mri_->reg_end()) {
+ MachineInstr* MI = &*RI;
+
+ SmallVector<unsigned, 2> Indices;
+ bool HasUse = false;
+ bool HasDef = false;
+
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& mop = MI->getOperand(i);
+ if (!mop.isReg() || mop.getReg() != li.reg) continue;
+
+ HasUse |= MI->getOperand(i).isUse();
+ HasDef |= MI->getOperand(i).isDef();
+
+ Indices.push_back(i);
+ }
+
+ if (!tryFoldMemoryOperand(MI, vrm, NULL, getInstructionIndex(MI),
+ Indices, true, slot, li.reg)) {
+ unsigned NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ vrm.assignVirt2StackSlot(NewVReg, slot);
+
+ // create a new register for this spill
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+
+ // the spill weight is now infinity as it
+ // cannot be spilled again
+ nI.weight = HUGE_VALF;
+
+ // Rewrite register operands to use the new vreg.
+ for (SmallVectorImpl<unsigned>::iterator I = Indices.begin(),
+ E = Indices.end(); I != E; ++I) {
+ MI->getOperand(*I).setReg(NewVReg);
+
+ if (MI->getOperand(*I).isUse())
+ MI->getOperand(*I).setIsKill(true);
+ }
+
+ // Fill in the new live interval.
+ unsigned index = getInstructionIndex(MI);
+ if (HasUse) {
+ LiveRange LR(getLoadIndex(index), getUseIndex(index),
+ nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ vrm.addRestorePoint(NewVReg, MI);
+ }
+ if (HasDef) {
+ LiveRange LR(getDefIndex(index), getStoreIndex(index),
+ nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ vrm.addSpillPoint(NewVReg, true, MI);
+ }
+
+ added.push_back(&nI);
+
+ DOUT << "\t\t\t\tadded new interval: ";
+ DEBUG(nI.dump());
+ DOUT << '\n';
+
+ unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
+ if (HasUse) {
+ if (HasDef)
+ SSWeight += getSpillWeight(true, true, loopDepth);
+ else
+ SSWeight += getSpillWeight(false, true, loopDepth);
+ } else
+ SSWeight += getSpillWeight(true, false, loopDepth);
+ }
+
+
+ RI = mri_->reg_begin(li.reg);
+ }
+
+ // Clients expect the new intervals to be returned in sorted order.
+ std::sort(added.begin(), added.end(), LISorter());
+
+ return added;
+}
+
+std::vector<LiveInterval*> LiveIntervals::
+addIntervalsForSpills(const LiveInterval &li,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
+ float &SSWeight) {
+
+ if (EnableFastSpilling)
+ return addIntervalsForSpillsFast(li, loopInfo, vrm, SSWeight);
+
assert(li.weight != HUGE_VALF &&
"attempt to spill already spilled interval!");
li.print(DOUT, tri_);
DOUT << '\n';
- // Each bit specify whether it a spill is required in the MBB.
+ // Spill slot weight.
+ SSWeight = 0.0f;
+
+ // Each bit specify whether a spill is required in the MBB.
BitVector SpillMBBs(mf_->getNumBlockIDs());
- std::map<unsigned, std::vector<SRInfo> > SpillIdxes;
+ DenseMap<unsigned, std::vector<SRInfo> > SpillIdxes;
BitVector RestoreMBBs(mf_->getNumBlockIDs());
- std::map<unsigned, std::vector<SRInfo> > RestoreIdxes;
- std::map<unsigned,unsigned> MBBVRegsMap;
+ DenseMap<unsigned, std::vector<SRInfo> > RestoreIdxes;
+ DenseMap<unsigned,unsigned> MBBVRegsMap;
std::vector<LiveInterval*> NewLIs;
const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
+ (DefIsReMat && (ReMatDefMI->getDesc().canFoldAsLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs);
+ MBBVRegsMap, NewLIs, SSWeight);
} else {
rewriteInstructionsForSpills(li, false, I, NULL, 0,
Slot, 0, false, false, false,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs);
+ MBBVRegsMap, NewLIs, SSWeight);
}
IsFirstRange = false;
}
+ SSWeight = 0.0f; // Already accounted for when split.
handleSpilledImpDefs(li, vrm, rc, NewLIs);
return NewLIs;
}
MachineInstr *ReMatDefMI = (DefIdx == ~0u)
? 0 : getInstructionFromIndex(DefIdx);
bool dummy;
- if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, dummy)) {
+ if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, SpillIs, dummy)) {
// Remember how to remat the def of this val#.
ReMatOrigDefs[VN] = ReMatDefMI;
- // Original def may be modified so we have to make a copy here. vrm must
- // delete these!
- ReMatDefs[VN] = ReMatDefMI = ReMatDefMI->clone();
+ // Original def may be modified so we have to make a copy here.
+ MachineInstr *Clone = mf_->CloneMachineInstr(ReMatDefMI);
+ ClonedMIs.push_back(Clone);
+ ReMatDefs[VN] = Clone;
bool CanDelete = true;
if (VNI->hasPHIKill) {
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
+ (DefIsReMat && ReMatDefMI->getDesc().canFoldAsLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs);
+ MBBVRegsMap, NewLIs, SSWeight);
}
// Insert spills / restores if we are splitting.
if (NeedStackSlot) {
int Id = SpillMBBs.find_first();
while (Id != -1) {
+ MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
std::vector<SRInfo> &spills = SpillIdxes[Id];
for (unsigned i = 0, e = spills.size(); i != e; ++i) {
int index = spills[i].index;
CanFold = true;
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
MachineOperand &MO = MI->getOperand(j);
- if (!MO.isRegister() || MO.getReg() != VReg)
+ if (!MO.isReg() || MO.getReg() != VReg)
continue;
Ops.push_back(j);
if (isKill)
AddedKill.insert(&nI);
}
+
+ // Update spill slot weight.
+ if (!isReMat)
+ SSWeight += getSpillWeight(true, false, loopDepth);
}
Id = SpillMBBs.find_next(Id);
}
int Id = RestoreMBBs.find_first();
while (Id != -1) {
+ MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+
std::vector<SRInfo> &restores = RestoreIdxes[Id];
for (unsigned i = 0, e = restores.size(); i != e; ++i) {
int index = restores[i].index;
continue;
unsigned VReg = restores[i].vreg;
LiveInterval &nI = getOrCreateInterval(VReg);
+ bool isReMat = vrm.isReMaterialized(VReg);
MachineInstr *MI = getInstructionFromIndex(index);
bool CanFold = false;
Ops.clear();
CanFold = true;
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
MachineOperand &MO = MI->getOperand(j);
- if (!MO.isRegister() || MO.getReg() != VReg)
+ if (!MO.isReg() || MO.getReg() != VReg)
continue;
if (MO.isDef()) {
// Fold the load into the use if possible.
bool Folded = false;
if (CanFold && !Ops.empty()) {
- if (!vrm.isReMaterialized(VReg))
+ if (!isReMat)
Folded = tryFoldMemoryOperand(MI, vrm, NULL,index,Ops,true,Slot,VReg);
else {
MachineInstr *ReMatDefMI = vrm.getReMaterializedMI(VReg);
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
- if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
+ if (isLoadSS || ReMatDefMI->getDesc().canFoldAsLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
- unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
- if (ImpUse) {
- // Re-matting an instruction with virtual register use. Add the
- // register as an implicit use on the use MI and update the register
- // interval's spill weight to HUGE_VALF to prevent it from being
- // spilled.
- LiveInterval &ImpLi = getInterval(ImpUse);
- ImpLi.weight = HUGE_VALF;
- MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+ if (!Folded) {
+ unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
+ if (ImpUse) {
+ // Re-matting an instruction with virtual register use. Add the
+ // register as an implicit use on the use MI and update the register
+ // interval's spill weight to HUGE_VALF to prevent it from being
+ // spilled.
+ LiveInterval &ImpLi = getInterval(ImpUse);
+ ImpLi.weight = HUGE_VALF;
+ MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+ }
}
}
}
nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
else
vrm.addRestorePoint(VReg, MI);
+
+ // Update spill slot weight.
+ if (!isReMat)
+ SSWeight += getSpillWeight(false, true, loopDepth);
}
Id = RestoreMBBs.find_next(Id);
}
for (unsigned i = 0, e = NewLIs.size(); i != e; ++i) {
LiveInterval *LI = NewLIs[i];
if (!LI->empty()) {
- LI->weight /= LI->getSize();
+ LI->weight /= InstrSlots::NUM * getApproximateInstructionCount(*LI);
if (!AddedKill.count(LI)) {
LiveRange *LR = &LI->ranges[LI->ranges.size()-1];
unsigned LastUseIdx = getBaseIndex(LR->end);
}
}
}
+
+LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
+ MachineInstr* startInst) {
+ LiveInterval& Interval = getOrCreateInterval(reg);
+ VNInfo* VN = Interval.getNextValue(
+ getInstructionIndex(startInst) + InstrSlots::DEF,
+ startInst, getVNInfoAllocator());
+ VN->hasPHIKill = true;
+ VN->kills.push_back(getMBBEndIdx(startInst->getParent()));
+ LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF,
+ getMBBEndIdx(startInst->getParent()) + 1, VN);
+ Interval.addRange(LR);
+
+ return LR;
+}
projects / oota-llvm.git / blobdiff