Spiller now remove unused spill slots.

[oota-llvm.git] / lib / CodeGen / LLVMTargetMachine.cpp

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index b50b2753922a9aeee887a2bc65356fe39ea758b5..5611b03ba764f2bc3aea397f91da7700753e39d2 100644 (file)
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -17,6 +17,7 @@
 #include "llvm/Assembly/PrintModulePass.h"
 #include "llvm/Analysis/LoopPass.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/Collector.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Support/CommandLine.h"
@@ -26,6 +27,25 @@ static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
     cl::desc("Print LLVM IR input to isel pass"));
+static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
+    cl::desc("Dump emitter generated instructions as assembly"));
+static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
+    cl::desc("Dump garbage collector data"));
+
+// Hidden options to help debugging
+static cl::opt<bool>
+EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
+              cl::desc("Perform sinking on machine code"));
+static cl::opt<bool>
+PerformLICM("machine-licm",
+            cl::init(false), cl::Hidden,
+            cl::desc("Perform loop-invariant code motion on machine code"));
+
+// When this works it will be on by default.
+static cl::opt<bool>
+DisablePostRAScheduler("disable-post-RA-scheduler",
+                       cl::desc("Disable scheduling after register allocation"),
+                       cl::init(true));
 
 FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
@@ -41,8 +61,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
   }
   
-  // FIXME: Implement efficient support for garbage collection intrinsics.
-  PM.add(createLowerGCPass());
+  PM.add(createGCLoweringPass());
 
   if (!ExceptionHandling)
     PM.add(createLowerInvokePass(getTargetLowering()));
@@ -64,12 +83,23 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+
+  if (PerformLICM)
+    PM.add(createMachineLICMPass());
   
+  if (EnableSinking)
+    PM.add(createMachineSinkingPass());
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+    
+  PM.add(createLowerSubregsPass());
+  
+  if (PrintMachineCode)  // Print the subreg lowered code
+    PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
@@ -79,12 +109,20 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   PM.add(createPrologEpilogCodeInserter());
   
   // Second pass scheduler.
-  PM.add(createPostRAScheduler());
+  if (!Fast && !DisablePostRAScheduler)
+    PM.add(createPostRAScheduler());
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
-    
+
+  PM.add(createGCMachineCodeAnalysisPass());
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+  
+  if (PrintGCInfo)
+    PM.add(createCollectorMetadataPrinter(*cerr));
+  
   // Fold redundant debug labels.
   PM.add(createDebugLabelFoldingPass());
   
@@ -118,7 +156,9 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
                                                   MachineCodeEmitter *MCE,
                                                   bool Fast) {
   if (MCE)
-    addSimpleCodeEmitter(PM, Fast, *MCE);
+    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
+    
+  PM.add(createCollectorMetadataDeleter());
 
   // Delete machine code for this function
   PM.add(createMachineCodeDeleter());
@@ -144,11 +184,10 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
   }
   
-  // FIXME: Implement efficient support for garbage collection intrinsics.
-  PM.add(createLowerGCPass());
+  PM.add(createGCLoweringPass());
   
-  // FIXME: Implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass(getTargetLowering()));
+  if (!ExceptionHandling)
+    PM.add(createLowerInvokePass(getTargetLowering()));
   
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
@@ -167,12 +206,23 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+
+  if (PerformLICM)
+    PM.add(createMachineLICMPass());
   
+  if (EnableSinking)
+    PM.add(createMachineSinkingPass());
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+    
+  PM.add(createLowerSubregsPass());
+  
+  if (PrintMachineCode)  // Print the subreg lowered code
+    PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
@@ -185,16 +235,26 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
     PM.add(createMachineFunctionPrinterPass(cerr));
   
   // Second pass scheduler.
-  PM.add(createPostRAScheduler());
+  if (!Fast)
+    PM.add(createPostRAScheduler());
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
+
+  PM.add(createGCMachineCodeAnalysisPass());
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+  
+  if (PrintGCInfo)
+    PM.add(createCollectorMetadataPrinter(*cerr));
   
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  addCodeEmitter(PM, Fast, MCE);
+  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
+  
+  PM.add(createCollectorMetadataDeleter());
   
   // Delete machine code for this function
   PM.add(createMachineCodeDeleter());