#include "SchedGraph.h"
#include "llvm/Function.h"
-#include "llvm/iOther.h"
-#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/Instructions.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegInfo.h"
-#include "Support/STLExtras.h"
+#include "../../Target/SparcV9/MachineCodeForInstruction.h"
+#include "../../Target/SparcV9/SparcV9RegInfo.h"
+#include "../../Target/SparcV9/SparcV9InstrInfo.h"
+#include "llvm/ADT/STLExtras.h"
+#include <iostream>
namespace llvm {
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
- MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
- if (MI) {
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
+ if (mbb) {
+ MachineBasicBlock::iterator I = MBB->begin();
+ std::advance(I, indexInBB);
+ MI = I;
+
MachineOpCode mopCode = MI->getOpcode();
- latency = Target.getInstrInfo().hasResultInterlock(mopCode)
- ? Target.getInstrInfo().minLatency(mopCode)
- : Target.getInstrInfo().maxLatency(mopCode);
+ latency = Target.getInstrInfo()->hasResultInterlock(mopCode)
+ ? Target.getInstrInfo()->minLatency(mopCode)
+ : Target.getInstrInfo()->maxLatency(mopCode);
}
}
void SchedGraph::dump() const {
std::cerr << " Sched Graph for Basic Block: "
<< MBB.getBasicBlock()->getName()
- << " (" << MBB.getBasicBlock() << ")"
+ << " (" << *MBB.getBasicBlock() << ")"
<< "\n\n Actual Root nodes: ";
for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(),
E = graphRoot->endOutEdges();
void SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
// Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again.
//
- for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (&MBB[i] == termMvec[first]) // reached the first branch
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
+ if (&*I == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
+ SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
- assert(i+d < N && "Insufficient delay slots for instruction?");
-
- for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
+ unsigned d = mii.getNumDelaySlots(I->getOpcode());
+
+ MachineBasicBlock::iterator J = I; ++J;
+ for (unsigned j=1; j <= d; j++, ++J) {
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
MachineOpCode opCode = node->getOpcode();
unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
- if (regNum != target.getRegInfo().getZeroRegNum())
+ if (regNum != target.getRegInfo()->getZeroRegNum())
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
{
unsigned rcid;
- int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
- if (target.getRegInfo().getMachineRegClass(rcid)
+ int regInClass = target.getRegInfo()->getClassRegNum(regNum, rcid);
+ if (target.getRegInfo()->getMachineRegClass(rcid)
->isRegVolatile(regInClass))
callDepNodeVec.push_back(node);
}
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
unsigned regNum = mop.getReg();
- if (regNum != target.getRegInfo().getZeroRegNum())
+ if (regNum != target.getRegInfo()->getZeroRegNum())
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = *target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
- for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
+ unsigned i = 0;
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
+ ++I, ++i)
+ if (I->getOpcode() != V9::PHI) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(&MBB[i], node);
+ noteGraphNodeForInstr(I, node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
this->addCallDepEdges(callDepNodeVec, target);
// Then add incoming def-use (SSA) edges for each machine instruction.
- for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
+ addEdgesForInstruction(*I, valueToDefVecMap, target);
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
os<< "Control Dep";
break;
case SchedGraphEdge::ValueDep:
- os<< "Reg Value " << val;
+ os<< "Reg Value " << *val;
break;
case SchedGraphEdge::MemoryDep:
os<< "Memory Dep";
projects / oota-llvm.git / blobdiff