#include "SchedPriorities.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
-#include "llvm/Instruction.h"
#include "Support/CommandLine.h"
#include <algorithm>
using std::cerr;
SchedDebugLevel_t SchedDebugLevel;
-static cl::Enum<enum SchedDebugLevel_t> Opt(SchedDebugLevel,"dsched",cl::Hidden,
- "enable instruction scheduling debugging information",
- clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
- clEnumValN(Sched_Disable, "off", "disable instruction scheduling"),
- clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
- clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
- clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
+static cl::opt<SchedDebugLevel_t, true>
+SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
+ cl::desc("enable instruction scheduling debugging information"),
+ cl::values(
+ clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
+ clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
+ clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
+ clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"),
+ 0));
//************************* Internal Data Types *****************************/
//----------------------------------------------------------------------
template<class _NodeType>
-class ScheduleIterator: public std::forward_iterator<_NodeType, ptrdiff_t> {
+class ScheduleIterator : public forward_iterator<_NodeType, ptrdiff_t> {
private:
unsigned cycleNum;
unsigned slotNum;
unsigned int totalInstrCount;
cycles_t curTime;
cycles_t nextEarliestIssueTime; // next cycle we can issue
- vector<std::hash_set<const SchedGraphNode*> > choicesForSlot; // indexed by slot#
+ vector<hash_set<const SchedGraphNode*> > choicesForSlot; // indexed by slot#
vector<const SchedGraphNode*> choiceVec; // indexed by node ptr
vector<int> numInClass; // indexed by sched class
vector<cycles_t> nextEarliestStartTime; // indexed by opCode
- std::hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
+ hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
// indexed by branch node ptr
public:
SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
SchedPriorities& schedPrio);
~SchedulingManager() {
- for (std::hash_map<const SchedGraphNode*,
+ for (hash_map<const SchedGraphNode*,
DelaySlotInfo*>::iterator I = delaySlotInfoForBranches.begin(),
E = delaySlotInfoForBranches.end(); I != E; ++I)
delete I->second;
return choiceVec[i];
}
- inline std::hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) {
+ inline hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) {
assert(slotNum < nslots);
return choicesForSlot[slotNum];
}
inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
bool createIfMissing=false)
{
- std::hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
+ hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
I = delaySlotInfoForBranches.find(bn);
if (I != delaySlotInfoForBranches.end())
return I->second;
curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
}
- const vector<MachineOpCode>*
+ const std::vector<MachineOpCode>&
conflictVec = schedInfo.getConflictList(node->getOpCode());
- if (conflictVec != NULL)
- for (unsigned i=0; i < conflictVec->size(); i++)
- {
- MachineOpCode toOp = (*conflictVec)[i];
- cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getOpCode(),
- toOp);
- assert(toOp < (int) nextEarliestStartTime.size());
- if (nextEarliestStartTime[toOp] < est)
- nextEarliestStartTime[toOp] = est;
- }
+ for (unsigned i=0; i < conflictVec.size(); i++)
+ {
+ MachineOpCode toOp = conflictVec[i];
+ cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpCode(),toOp);
+ assert(toOp < (int) nextEarliestStartTime.size());
+ if (nextEarliestStartTime[toOp] < est)
+ nextEarliestStartTime[toOp] = est;
+ }
}
//************************* Internal Functions *****************************/
static void
RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
{
- MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
+ MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
- for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
+ for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
if (! mii.isNop((*I)->getOpCode()) &&
! mii.isDummyPhiInstr((*I)->getOpCode()))
++numInstr;
return; // empty basic block!
// First find the dummy instructions at the start of the basic block
- MachineCodeForBasicBlock::iterator I = mvec.begin();
+ MachineBasicBlock::iterator I = mvec.begin();
for ( ; I != mvec.end(); ++I)
if (! mii.isDummyPhiInstr((*I)->getOpCode()))
break;
// fill delay slots, otherwise, just discard them.
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
- MachineCodeForBasicBlock& bbMvec = node->getBB()->getMachineInstrVec();
+ MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
if (sdelayNodeVec.size() < ndelays)
sdelayNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
else
- nopNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
-
+ {
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
+
+ //remove the MI from the Machine Code For Instruction
+ MachineCodeForInstruction& llvmMvec =
+ MachineCodeForInstruction::get((Instruction *)
+ (node->getBB()->getTerminator()));
+ for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
+ mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
+ if(*mciI==bbMvec[i])
+ llvmMvec.erase(mciI);
+ }
+ }
+
assert(sdelayNodeVec.size() >= ndelays);
// If some delay slots were already filled, throw away that many new choices
// Simply passing in an empty delayNodeVec will have this effect.
//
delayNodeVec.clear();
- const MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
- for (unsigned i=0; i < bbMvec.size(); i++)
+ const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
+ for (unsigned i=0; i < bbMvec.size(); ++i)
if (bbMvec[i] != brInstr &&
mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
{
// getAnalysisUsage - We use LiveVarInfo...
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired(FunctionLiveVarInfo::ID);
+ AU.addRequired<FunctionLiveVarInfo>();
+ AU.setPreservesCFG();
}
bool runOnFunction(Function &F);
bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
{
- if (SchedDebugLevel == Sched_Disable)
- return false;
-
SchedGraphSet graphSet(&F, target);
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
if (SchedDebugLevel >= Sched_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
- MachineCodeForMethod::get(&F).dump();
+ MachineFunction::get(&F).dump();
}
return false;
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