//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_CODEGEN_ALLOCATIONORDER_H
-#define LLVM_CODEGEN_ALLOCATIONORDER_H
+#ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
+#define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
-#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/MC/MCRegisterInfo.h"
namespace llvm {
class AllocationOrder {
SmallVector<MCPhysReg, 16> Hints;
ArrayRef<MCPhysReg> Order;
- unsigned Pos;
+ int Pos;
public:
/// Create a new AllocationOrder for VirtReg.
const VirtRegMap &VRM,
const RegisterClassInfo &RegClassInfo);
+ /// Get the allocation order without reordered hints.
+ ArrayRef<MCPhysReg> getOrder() const { return Order; }
+
/// Return the next physical register in the allocation order, or 0.
/// It is safe to call next() again after it returned 0, it will keep
/// returning 0 until rewind() is called.
- unsigned next();
+ unsigned next(unsigned Limit = 0) {
+ if (Pos < 0)
+ return Hints.end()[Pos++];
+ if (!Limit)
+ Limit = Order.size();
+ while (Pos < int(Limit)) {
+ unsigned Reg = Order[Pos++];
+ if (!isHint(Reg))
+ return Reg;
+ }
+ return 0;
+ }
+
+ /// As next(), but allow duplicates to be returned, and stop before the
+ /// Limit'th register in the RegisterClassInfo allocation order.
+ ///
+ /// This can produce more than Limit registers if there are hints.
+ unsigned nextWithDups(unsigned Limit) {
+ if (Pos < 0)
+ return Hints.end()[Pos++];
+ if (Pos < int(Limit))
+ return Order[Pos++];
+ return 0;
+ }
/// Start over from the beginning.
- void rewind() { Pos = 0; }
+ void rewind() { Pos = -int(Hints.size()); }
/// Return true if the last register returned from next() was a preferred register.
- bool isHint() const { return Pos <= Hints.size(); }
+ bool isHint() const { return Pos <= 0; }
/// Return true if PhysReg is a preferred register.
- bool isHint(unsigned PhysReg) const;
+ bool isHint(unsigned PhysReg) const {
+ return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
+ }
};
} // end namespace llvm