//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "AllocationOrder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
// Compare VirtRegMap::getRegAllocPref().
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+ rewind();
DEBUG({
if (!Hints.empty()) {
dbgs() << '\n';
}
});
-}
-
-bool AllocationOrder::isHint(unsigned PhysReg) const {
- return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
-}
-
-unsigned AllocationOrder::next() {
- if (Pos < Hints.size())
- return Hints[Pos++];
- ArrayRef<MCPhysReg>::iterator I = Order.begin() + (Pos - Hints.size());
- ArrayRef<MCPhysReg>::iterator E = Order.end();
- while (I != E) {
- unsigned Reg = *I++;
- ++Pos;
- if (!isHint(Reg))
- return Reg;
- }
- return 0;
+#ifndef NDEBUG
+ for (unsigned I = 0, E = Hints.size(); I != E; ++I)
+ assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
+ "Target hint is outside allocation order.");
+#endif
}