Revert "[AArch64] Enable PostRAScheduler for AArch64 generic build"

[oota-llvm.git] / lib / CodeGen / AllocationOrder.cpp

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index a76791025d9a013f6f42017460779239b8e3553b..40451c0d6c19dcaf8230b63ad714554f8e3c33bd 100644 (file)
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -14,7 +14,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "regalloc"
 #include "AllocationOrder.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -22,19 +21,22 @@
 #include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 
+#define DEBUG_TYPE "regalloc"
+
 // Compare VirtRegMap::getRegAllocPref().
 AllocationOrder::AllocationOrder(unsigned VirtReg,
                                  const VirtRegMap &VRM,
-                                 const RegisterClassInfo &RegClassInfo)
+                                 const RegisterClassInfo &RegClassInfo,
+                                 const LiveRegMatrix *Matrix)
   : Pos(0) {
   const MachineFunction &MF = VRM.getMachineFunction();
   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
   Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
-  TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+  TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
+  rewind();
 
   DEBUG({
     if (!Hints.empty()) {
@@ -44,22 +46,9 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
       dbgs() << '\n';
     }
   });
-}
-
-bool AllocationOrder::isHint(unsigned PhysReg) const {
-  return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
-}
-
-unsigned AllocationOrder::next() {
-  if (Pos < Hints.size())
-    return Hints[Pos++];
-  ArrayRef<MCPhysReg>::iterator I = Order.begin() + (Pos - Hints.size());
-  ArrayRef<MCPhysReg>::iterator E = Order.end();
-  while (I != E) {
-    unsigned Reg = *I++;
-    ++Pos;
-    if (!isHint(Reg))
-      return Reg;
-  }
-  return 0;
+#ifndef NDEBUG
+  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
+    assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
+           "Target hint is outside allocation order.");
+#endif
 }