#ifndef LLVM_TARGET_TARGETMACHINE_H
#define LLVM_TARGET_TARGETMACHINE_H
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/CodeGen.h"
+#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <string>
class InstrItineraryData;
class JITCodeEmitter;
+class GlobalValue;
+class Mangler;
class MCAsmInfo;
+class MCCodeGenInfo;
class MCContext;
-class Pass;
-class PassManager;
-class PassManagerBase;
+class MCSymbol;
class Target;
-class TargetData;
-class TargetELFWriterInfo;
+class DataLayout;
+class TargetLibraryInfo;
class TargetFrameLowering;
-class TargetInstrInfo;
class TargetIntrinsicInfo;
class TargetJITInfo;
class TargetLowering;
+class TargetPassConfig;
class TargetRegisterInfo;
class TargetSelectionDAGInfo;
class TargetSubtargetInfo;
+class ScalarTargetTransformInfo;
+class VectorTargetTransformInfo;
class formatted_raw_ostream;
class raw_ostream;
-// Relocation model types.
-namespace Reloc {
- enum Model {
- Default,
- Static,
- PIC_, // Cannot be named PIC due to collision with -DPIC
- DynamicNoPIC
- };
-}
-
-// Code model types.
-namespace CodeModel {
- enum Model {
- Default,
- Small,
- Kernel,
- Medium,
- Large
- };
-}
-
-// Code generation optimization level.
-namespace CodeGenOpt {
- enum Level {
- None, // -O0
- Less, // -O1
- Default, // -O2, -Os
- Aggressive // -O3
- };
-}
-
-namespace Sched {
- enum Preference {
- None, // No preference
- Latency, // Scheduling for shortest total latency.
- RegPressure, // Scheduling for lowest register pressure.
- Hybrid, // Scheduling for both latency and register pressure.
- ILP // Scheduling for ILP in low register pressure mode.
- };
+// The old pass manager infrastructure is hidden in a legacy namespace now.
+namespace legacy {
+class PassManagerBase;
}
+using legacy::PassManagerBase;
//===----------------------------------------------------------------------===//
///
/// through this interface.
///
class TargetMachine {
- TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
- void operator=(const TargetMachine &); // DO NOT IMPLEMENT
+ TargetMachine(const TargetMachine &) LLVM_DELETED_FUNCTION;
+ void operator=(const TargetMachine &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses.
- TargetMachine(const Target &);
-
- /// getSubtargetImpl - virtual method implemented by subclasses that returns
- /// a reference to that target's TargetSubtargetInfo-derived member variable.
- virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
+ TargetMachine(const Target &T, StringRef TargetTriple,
+ StringRef CPU, StringRef FS, const TargetOptions &Options);
/// TheTarget - The Target that this machine was created for.
const Target &TheTarget;
+ /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
+ /// feature strings the TargetMachine instance is created with.
+ std::string TargetTriple;
+ std::string TargetCPU;
+ std::string TargetFS;
+
+ /// CodeGenInfo - Low level target information such as relocation model.
+ /// Non-const to allow resetting optimization level per-function.
+ MCCodeGenInfo *CodeGenInfo;
+
/// AsmInfo - Contains target specific asm information.
///
const MCAsmInfo *AsmInfo;
- unsigned MCRelaxAll : 1;
- unsigned MCNoExecStack : 1;
- unsigned MCSaveTempLabels : 1;
- unsigned MCUseLoc : 1;
- unsigned MCUseCFI : 1;
+ unsigned RequireStructuredCFG : 1;
public:
virtual ~TargetMachine();
const Target &getTarget() const { return TheTarget; }
- // Interfaces to the major aspects of target machine information:
- // -- Instruction opcode and operand information
- // -- Pipelines and scheduling information
- // -- Stack frame information
- // -- Selection DAG lowering information
- //
- virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
- virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
- virtual const TargetLowering *getTargetLowering() const { return 0; }
- virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
- virtual const TargetData *getTargetData() const { return 0; }
+ const StringRef getTargetTriple() const { return TargetTriple; }
+ const StringRef getTargetCPU() const { return TargetCPU; }
+ const StringRef getTargetFeatureString() const { return TargetFS; }
+
+ /// getSubtargetImpl - virtual method implemented by subclasses that returns
+ /// a reference to that target's TargetSubtargetInfo-derived member variable.
+ virtual const TargetSubtargetInfo *getSubtargetImpl() const {
+ return nullptr;
+ }
+ virtual TargetSubtargetInfo *getSubtargetImpl() {
+ const TargetMachine *TM = this;
+ return const_cast<TargetSubtargetInfo *>(TM->getSubtargetImpl());
+ }
+
+ mutable TargetOptions Options;
+
+ /// \brief Reset the target options based on the function's attributes.
+ void resetTargetOptions(const MachineFunction *MF) const;
/// getMCAsmInfo - Return target specific asm information.
///
return *static_cast<const STC*>(getSubtargetImpl());
}
- /// getRegisterInfo - If register information is available, return it. If
- /// not, return null. This is kept separate from RegInfo until RegInfo has
- /// details of graph coloring register allocation removed from it.
- ///
- virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
-
/// getIntrinsicInfo - If intrinsic information is available, return it. If
/// not, return null.
///
- virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
-
- /// getJITInfo - If this target supports a JIT, return information for it,
- /// otherwise return null.
- ///
- virtual TargetJITInfo *getJITInfo() { return 0; }
-
- /// getInstrItineraryData - Returns instruction itinerary data for the target
- /// or specific subtarget.
- ///
- virtual const InstrItineraryData *getInstrItineraryData() const {
- return 0;
+ virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
+ return nullptr;
}
- /// getELFWriterInfo - If this target supports an ELF writer, return
- /// information for it, otherwise return null.
- ///
- virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
-
- /// hasMCRelaxAll - Check whether all machine code instructions should be
- /// relaxed.
- bool hasMCRelaxAll() const { return MCRelaxAll; }
-
- /// setMCRelaxAll - Set whether all machine code instructions should be
- /// relaxed.
- void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
-
- /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
- /// (i.e., not treated as temporary).
- bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
-
- /// setMCSaveTempLabels - Set whether temporary labels will be preserved
- /// (i.e., not treated as temporary).
- void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
-
- /// hasMCNoExecStack - Check whether an executable stack is not needed.
- bool hasMCNoExecStack() const { return MCNoExecStack; }
-
- /// setMCNoExecStack - Set whether an executabel stack is not needed.
- void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
-
- /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
- bool hasMCUseLoc() const { return MCUseLoc; }
-
- /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
- void setMCUseLoc(bool Value) { MCUseLoc = Value; }
-
- /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
- bool hasMCUseCFI() const { return MCUseCFI; }
-
- /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
- void setMCUseCFI(bool Value) { MCUseCFI = Value; }
+ bool requiresStructuredCFG() const { return RequireStructuredCFG; }
+ void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
- static Reloc::Model getRelocationModel();
-
- /// setRelocationModel - Sets the code generation relocation model.
- ///
- static void setRelocationModel(Reloc::Model Model);
+ Reloc::Model getRelocationModel() const;
/// getCodeModel - Returns the code model. The choices are small, kernel,
/// medium, large, and target default.
- static CodeModel::Model getCodeModel();
+ CodeModel::Model getCodeModel() const;
- /// setCodeModel - Sets the code model.
- ///
- static void setCodeModel(CodeModel::Model Model);
+ /// getTLSModel - Returns the TLS model which should be used for the given
+ /// global variable.
+ TLSModel::Model getTLSModel(const GlobalValue *GV) const;
+
+ /// getOptLevel - Returns the optimization level: None, Less,
+ /// Default, or Aggressive.
+ CodeGenOpt::Level getOptLevel() const;
+
+ /// \brief Overrides the optimization level.
+ void setOptLevel(CodeGenOpt::Level Level) const;
+
+ void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
+
+ bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
///
- static bool getAsmVerbosityDefault();
+ bool getAsmVerbosityDefault() const ;
/// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
/// is false.
- static void setAsmVerbosityDefault(bool);
+ void setAsmVerbosityDefault(bool);
/// getDataSections - Return true if data objects should be emitted into their
/// own section, corresponds to -fdata-sections.
- static bool getDataSections();
+ bool getDataSections() const;
/// getFunctionSections - Return true if functions should be emitted into
/// their own section, corresponding to -ffunction-sections.
- static bool getFunctionSections();
+ bool getFunctionSections() const;
/// setDataSections - Set if the data are emit into separate sections.
- static void setDataSections(bool);
+ void setDataSections(bool);
/// setFunctionSections - Set if the functions are emit into separate
/// sections.
- static void setFunctionSections(bool);
+ void setFunctionSections(bool);
+
+ /// \brief Register analysis passes for this target with a pass manager.
+ virtual void addAnalysisPasses(PassManagerBase &) {}
/// CodeGenFileType - These enums are meant to be passed into
/// addPassesToEmitFile to indicate what type of file to emit, and returned by
CGFT_Null // Do not emit any output.
};
- /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
- /// on this target. User flag overrides.
- virtual bool getEnableTailMergeDefault() const { return true; }
-
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
/// generation. This method should return true if emission of this file type
virtual bool addPassesToEmitFile(PassManagerBase &,
formatted_raw_ostream &,
CodeGenFileType,
- CodeGenOpt::Level,
- bool = true) {
+ bool /*DisableVerify*/ = true,
+ AnalysisID /*StartAfter*/ = nullptr,
+ AnalysisID /*StopAfter*/ = nullptr) {
return true;
}
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
JITCodeEmitter &,
- CodeGenOpt::Level,
- bool = true) {
+ bool /*DisableVerify*/ = true) {
return true;
}
virtual bool addPassesToEmitMC(PassManagerBase &,
MCContext *&,
raw_ostream &,
- CodeGenOpt::Level,
- bool = true) {
+ bool /*DisableVerify*/ = true) {
return true;
}
+
+ void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
+ Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
+ MCSymbol *getSymbol(const GlobalValue *GV, Mangler &Mang) const;
};
/// LLVMTargetMachine - This class describes a target machine that is
/// implemented with the LLVM target-independent code generator.
///
class LLVMTargetMachine : public TargetMachine {
- std::string TargetTriple;
-
protected: // Can only create subclasses.
- LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
-
-private:
- /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
- /// both emitting to assembly files or machine code output.
- ///
- bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
- bool DisableVerify, MCContext *&OutCtx);
-
- virtual void setCodeModelForJIT();
- virtual void setCodeModelForStatic();
+ LLVMTargetMachine(const Target &T, StringRef TargetTriple,
+ StringRef CPU, StringRef FS, TargetOptions Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+ void initAsmInfo();
public:
+ /// \brief Register analysis passes for this target with a pass manager.
+ ///
+ /// This registers target independent analysis passes.
+ void addAnalysisPasses(PassManagerBase &PM) override;
- const std::string &getTargetTriple() const { return TargetTriple; }
+ /// createPassConfig - Create a pass configuration object to be used by
+ /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
- /// generation. If OptLevel is None, the code generator should emit code as
- /// fast as possible, though the generated code may be less efficient.
- virtual bool addPassesToEmitFile(PassManagerBase &PM,
- formatted_raw_ostream &Out,
- CodeGenFileType FileType,
- CodeGenOpt::Level,
- bool DisableVerify = true);
+ /// generation.
+ bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
+ CodeGenFileType FileType, bool DisableVerify = true,
+ AnalysisID StartAfter = nullptr,
+ AnalysisID StopAfter = nullptr) override;
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
/// get machine code emitted. This uses a JITCodeEmitter object to handle
/// of functions. This method returns true if machine code emission is
/// not supported.
///
- virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
- JITCodeEmitter &MCE,
- CodeGenOpt::Level,
- bool DisableVerify = true);
+ bool addPassesToEmitMachineCode(PassManagerBase &PM, JITCodeEmitter &MCE,
+ bool DisableVerify = true) override;
/// addPassesToEmitMC - Add passes to the specified pass manager to get
/// machine code emitted with the MCJIT. This method returns true if machine
/// code is not supported. It fills the MCContext Ctx pointer which can be
/// used to build custom MCStreamer.
///
- virtual bool addPassesToEmitMC(PassManagerBase &PM,
- MCContext *&Ctx,
- raw_ostream &OS,
- CodeGenOpt::Level OptLevel,
- bool DisableVerify = true);
-
- /// Target-Independent Code Generator Pass Configuration Options.
-
- /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
- /// passes (which are run just before instruction selector).
- virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
- return true;
- }
-
- /// addInstSelector - This method should install an instruction selector pass,
- /// which converts from LLVM code to machine instructions.
- virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
- return true;
- }
-
- /// addPreRegAlloc - This method may be implemented by targets that want to
- /// run passes immediately before register allocation. This should return
- /// true if -print-machineinstrs should print after these passes.
- virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
- return false;
- }
-
- /// addPostRegAlloc - This method may be implemented by targets that want
- /// to run passes after register allocation but before prolog-epilog
- /// insertion. This should return true if -print-machineinstrs should print
- /// after these passes.
- virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
- return false;
- }
-
- /// addPreSched2 - This method may be implemented by targets that want to
- /// run passes after prolog-epilog insertion and before the second instruction
- /// scheduling pass. This should return true if -print-machineinstrs should
- /// print after these passes.
- virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
- return false;
- }
-
- /// addPreEmitPass - This pass may be implemented by targets that want to run
- /// passes immediately before machine code is emitted. This should return
- /// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
- return false;
- }
-
+ bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
+ raw_ostream &OS, bool DisableVerify = true) override;
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned.
- virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
+ virtual bool addCodeEmitter(PassManagerBase &,
JITCodeEmitter &) {
return true;
}
-
- /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
- /// on this target. User flag overrides.
- virtual bool getEnableTailMergeDefault() const { return true; }
};
} // End llvm namespace
projects / oota-llvm.git / blobdiff