//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file describes the general parts of a Target machine.
+// This file defines the TargetMachine and LLVMTargetMachine classes.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETMACHINE_H
#define LLVM_TARGET_TARGETMACHINE_H
-#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetInstrItineraries.h"
#include <cassert>
+#include <string>
namespace llvm {
+class Target;
+class MCAsmInfo;
+class TargetData;
+class TargetSubtarget;
class TargetInstrInfo;
-class TargetInstrDescriptor;
+class TargetIntrinsicInfo;
class TargetJITInfo;
-class TargetSchedInfo;
-class SparcV9RegInfo;
+class TargetLowering;
class TargetFrameInfo;
-class MachineCodeEmitter;
-class MRegisterInfo;
-class FunctionPassManager;
+class JITCodeEmitter;
+class TargetRegisterInfo;
+class PassManagerBase;
class PassManager;
class Pass;
-class IntrinsicLowering;
+class TargetELFWriterInfo;
+class formatted_raw_ostream;
+
+// Relocation model types.
+namespace Reloc {
+ enum Model {
+ Default,
+ Static,
+ PIC_, // Cannot be named PIC due to collision with -DPIC
+ DynamicNoPIC
+ };
+}
+
+// Code model types.
+namespace CodeModel {
+ enum Model {
+ Default,
+ Small,
+ Kernel,
+ Medium,
+ Large
+ };
+}
+
+// Code generation optimization level.
+namespace CodeGenOpt {
+ enum Level {
+ None, // -O0
+ Less, // -O1
+ Default, // -O2, -Os
+ Aggressive // -O3
+ };
+}
//===----------------------------------------------------------------------===//
///
/// through this interface.
///
class TargetMachine {
- const std::string Name;
- const TargetData DataLayout; // Calculates type size & alignment
- IntrinsicLowering *IL; // Specifies how to lower intrinsic calls
-
- TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT
- void operator=(const TargetMachine&); // DO NOT IMPLEMENT
-protected: // Can only create subclasses...
- TargetMachine(const std::string &name, IntrinsicLowering *IL,
- bool LittleEndian = false,
- unsigned char PtrSize = 8, unsigned char PtrAl = 8,
- unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
- unsigned char LongAl = 8, unsigned char IntAl = 4,
- unsigned char ShortAl = 2, unsigned char ByteAl = 1,
- unsigned char BoolAl = 1);
-
- TargetMachine(const std::string &name, IntrinsicLowering *IL,
- const TargetData &TD);
-
- /// This constructor is used for targets that support arbitrary TargetData
- /// layouts, like the C backend. It initializes the TargetData to match that
- /// of the specified module.
+ TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
+ void operator=(const TargetMachine &); // DO NOT IMPLEMENT
+protected: // Can only create subclasses.
+ TargetMachine(const Target &);
+
+ /// getSubtargetImpl - virtual method implemented by subclasses that returns
+ /// a reference to that target's TargetSubtarget-derived member variable.
+ virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
+
+ /// TheTarget - The Target that this machine was created for.
+ const Target &TheTarget;
+
+ /// AsmInfo - Contains target specific asm information.
///
- TargetMachine(const std::string &name, IntrinsicLowering *IL,
- const Module &M);
+ const MCAsmInfo *AsmInfo;
+
public:
virtual ~TargetMachine();
- /// getModuleMatchQuality - This static method should be implemented by
- /// targets to indicate how closely they match the specified module. This is
- /// used by the LLC tool to determine which target to use when an explicit
- /// -march option is not specified. If a target returns zero, it will never
- /// be chosen without an explicit -march option.
- static unsigned getModuleMatchQuality(const Module &M) { return 0; }
-
- /// getJITMatchQuality - This static method should be implemented by targets
- /// that provide JIT capabilities to indicate how suitable they are for
- /// execution on the current host. If a value of 0 is returned, the target
- /// will not be used unless an explicit -march option is used.
- static unsigned getJITMatchQuality() { return 0; }
-
-
- const std::string &getName() const { return Name; }
-
- /// getIntrinsicLowering - This method returns a reference to an
- /// IntrinsicLowering instance which should be used by the code generator to
- /// lower unknown intrinsic functions to the equivalent LLVM expansion.
- ///
- IntrinsicLowering &getIntrinsicLowering() const { return *IL; }
+ const Target &getTarget() const { return TheTarget; }
// Interfaces to the major aspects of target machine information:
// -- Instruction opcode and operand information
// -- Pipelines and scheduling information
// -- Stack frame information
+ // -- Selection DAG lowering information
//
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
- const TargetData &getTargetData() const { return DataLayout; }
+ virtual TargetLowering *getTargetLowering() const { return 0; }
+ virtual const TargetData *getTargetData() const { return 0; }
+
+ /// getMCAsmInfo - Return target specific asm information.
+ ///
+ const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
+
+ /// getSubtarget - This method returns a pointer to the specified type of
+ /// TargetSubtarget. In debug builds, it verifies that the object being
+ /// returned is of the correct type.
+ template<typename STC> const STC &getSubtarget() const {
+ return *static_cast<const STC*>(getSubtargetImpl());
+ }
/// getRegisterInfo - If register information is available, return it. If
/// not, return null. This is kept separate from RegInfo until RegInfo has
/// details of graph coloring register allocation removed from it.
///
- virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
+ virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
+
+ /// getIntrinsicInfo - If intrinsic information is available, return it. If
+ /// not, return null.
+ ///
+ virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
/// getJITInfo - If this target supports a JIT, return information for it,
/// otherwise return null.
///
virtual TargetJITInfo *getJITInfo() { return 0; }
+
+ /// getInstrItineraryData - Returns instruction itinerary data for the target
+ /// or specific subtarget.
+ ///
+ virtual const InstrItineraryData getInstrItineraryData() const {
+ return InstrItineraryData();
+ }
+
+ /// getELFWriterInfo - If this target supports an ELF writer, return
+ /// information for it, otherwise return null.
+ ///
+ virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
+
+ /// getRelocationModel - Returns the code generation relocation model. The
+ /// choices are static, PIC, and dynamic-no-pic, and target default.
+ static Reloc::Model getRelocationModel();
+
+ /// setRelocationModel - Sets the code generation relocation model.
+ ///
+ static void setRelocationModel(Reloc::Model Model);
+
+ /// getCodeModel - Returns the code model. The choices are small, kernel,
+ /// medium, large, and target default.
+ static CodeModel::Model getCodeModel();
+
+ /// setCodeModel - Sets the code model.
+ ///
+ static void setCodeModel(CodeModel::Model Model);
+
+ /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
+ ///
+ static bool getAsmVerbosityDefault();
- // These are deprecated interfaces.
- virtual const TargetSchedInfo *getSchedInfo() const { return 0; }
- virtual const SparcV9RegInfo *getRegInfo() const { return 0; }
+ /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
+ /// is false.
+ static void setAsmVerbosityDefault(bool);
/// CodeGenFileType - These enums are meant to be passed into
- /// addPassesToEmitFile to indicate what type of file to emit.
+ /// addPassesToEmitFile to indicate what type of file to emit, and returned by
+ /// it to indicate what type of file could actually be made.
enum CodeGenFileType {
- AssemblyFile
+ CGFT_AssemblyFile,
+ CGFT_ObjectFile,
+ CGFT_Null // Do not emit any output.
};
- /// addPassesToEmitFile - Add passes to the specified pass manager to get
- /// the specified file emitted. Typically this will involve several steps of
- /// code generation. This method should return true if emission of this file
- /// type is not supported.
+ /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
+ /// on this target. User flag overrides.
+ virtual bool getEnableTailMergeDefault() const { return true; }
+
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of code
+ /// generation. This method should return true if emission of this file type
+ /// is not supported, or false on success.
+ virtual bool addPassesToEmitFile(PassManagerBase &,
+ formatted_raw_ostream &,
+ CodeGenFileType,
+ CodeGenOpt::Level,
+ bool DisableVerify = true) {
+ return true;
+ }
+
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+ /// get machine code emitted. This uses a JITCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions. This method returns true if machine code emission is
+ /// not supported.
///
- virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
- CodeGenFileType FileType) {
+ virtual bool addPassesToEmitMachineCode(PassManagerBase &,
+ JITCodeEmitter &,
+ CodeGenOpt::Level,
+ bool DisableVerify = true) {
+ return true;
+ }
+
+ /// addPassesToEmitWholeFile - This method can be implemented by targets that
+ /// require having the entire module at once. This is not recommended, do not
+ /// use this.
+ virtual bool WantsWholeFile() const { return false; }
+ virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
+ CodeGenFileType,
+ CodeGenOpt::Level,
+ bool DisableVerify = true) {
return true;
}
+};
+
+/// LLVMTargetMachine - This class describes a target machine that is
+/// implemented with the LLVM target-independent code generator.
+///
+class LLVMTargetMachine : public TargetMachine {
+protected: // Can only create subclasses.
+ LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
+
+ /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
+ /// both emitting to assembly files or machine code output.
+ ///
+ bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+ bool DisableVerify);
+private:
+ virtual void setCodeModelForJIT();
+ virtual void setCodeModelForStatic();
+
+public:
+
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of code
+ /// generation. If OptLevel is None, the code generator should emit code as
+ /// fast as possible, though the generated code may be less efficient.
+ virtual bool addPassesToEmitFile(PassManagerBase &PM,
+ formatted_raw_ostream &Out,
+ CodeGenFileType FileType,
+ CodeGenOpt::Level,
+ bool DisableVerify = true);
+
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// get machine code emitted. This uses a JITCodeEmitter object to handle
/// actually outputting the machine code and resolving things like the address
- /// of functions. This method should returns true if machine code emission is
+ /// of functions. This method returns true if machine code emission is
/// not supported.
///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE) {
+ virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
+ JITCodeEmitter &MCE,
+ CodeGenOpt::Level,
+ bool DisableVerify = true);
+
+ /// Target-Independent Code Generator Pass Configuration Options.
+
+ /// addInstSelector - This method should add any "last minute" LLVM->LLVM
+ /// passes, then install an instruction selector pass, which converts from
+ /// LLVM code to machine instructions.
+ virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
+
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
+ /// true if -print-machineinstrs should print after these passes.
+ virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+ /// addPostRegAlloc - This method may be implemented by targets that want
+ /// to run passes after register allocation but before prolog-epilog
+ /// insertion. This should return true if -print-machineinstrs should print
+ /// after these passes.
+ virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+ /// addPreEmitPass - This pass may be implemented by targets that want to run
+ /// passes immediately before machine code is emitted. This should return
+ /// true if -print-machineinstrs should print out the code after the passes.
+ virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+
+ /// addCodeEmitter - This pass should be overridden by the target to add a
+ /// code emitter, if supported. If this is not supported, 'true' should be
+ /// returned.
+ virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
+ JITCodeEmitter &) {
+ return true;
+ }
+
+ /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
+ /// on this target. User flag overrides.
+ virtual bool getEnableTailMergeDefault() const { return true; }
};
} // End llvm namespace
projects / oota-llvm.git / blobdiff