//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
namespace llvm {
-class TargetAsmInfo;
+class Target;
+class MCAsmInfo;
class TargetData;
class TargetSubtarget;
class TargetInstrInfo;
-class TargetInstrDescriptor;
+class TargetIntrinsicInfo;
class TargetJITInfo;
class TargetLowering;
+class TargetSelectionDAGInfo;
class TargetFrameInfo;
-class MachineCodeEmitter;
-class MRegisterInfo;
-class Module;
-class FunctionPassManager;
+class JITCodeEmitter;
+class MCContext;
+class TargetRegisterInfo;
+class PassManagerBase;
class PassManager;
class Pass;
+class TargetELFWriterInfo;
+class formatted_raw_ostream;
// Relocation model types.
namespace Reloc {
};
}
+// Code generation optimization level.
+namespace CodeGenOpt {
+ enum Level {
+ None, // -O0
+ Less, // -O1
+ Default, // -O2, -Os
+ Aggressive // -O3
+ };
+}
+
+namespace Sched {
+ enum Preference {
+ None, // No preference
+ Latency, // Scheduling for shortest total latency.
+ RegPressure, // Scheduling for lowest register pressure.
+ Hybrid // Scheduling for both latency and register pressure.
+ };
+}
+
//===----------------------------------------------------------------------===//
///
/// TargetMachine - Primary interface to the complete machine description for
TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
void operator=(const TargetMachine &); // DO NOT IMPLEMENT
protected: // Can only create subclasses.
- TargetMachine() : AsmInfo(NULL) { }
+ TargetMachine(const Target &);
/// getSubtargetImpl - virtual method implemented by subclasses that returns
/// a reference to that target's TargetSubtarget-derived member variable.
virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
+
+ /// TheTarget - The Target that this machine was created for.
+ const Target &TheTarget;
/// AsmInfo - Contains target specific asm information.
///
- mutable const TargetAsmInfo *AsmInfo;
-
- /// createTargetAsmInfo - Create a new instance of target specific asm
- /// information.
- virtual const TargetAsmInfo *createTargetAsmInfo() const { return NULL; }
+ const MCAsmInfo *AsmInfo;
+
+ unsigned MCRelaxAll : 1;
public:
virtual ~TargetMachine();
- /// getModuleMatchQuality - This static method should be implemented by
- /// targets to indicate how closely they match the specified module. This is
- /// used by the LLC tool to determine which target to use when an explicit
- /// -march option is not specified. If a target returns zero, it will never
- /// be chosen without an explicit -march option.
- static unsigned getModuleMatchQuality(const Module &M) { return 0; }
-
- /// getJITMatchQuality - This static method should be implemented by targets
- /// that provide JIT capabilities to indicate how suitable they are for
- /// execution on the current host. If a value of 0 is returned, the target
- /// will not be used unless an explicit -march option is used.
- static unsigned getJITMatchQuality() { return 0; }
+ const Target &getTarget() const { return TheTarget; }
// Interfaces to the major aspects of target machine information:
// -- Instruction opcode and operand information
//
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
- virtual TargetLowering *getTargetLowering() const { return 0; }
+ virtual const TargetLowering *getTargetLowering() const { return 0; }
+ virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
virtual const TargetData *getTargetData() const { return 0; }
-
- /// getTargetAsmInfo - Return target specific asm information.
+ /// getMCAsmInfo - Return target specific asm information.
///
- const TargetAsmInfo *getTargetAsmInfo() const {
- if (!AsmInfo) AsmInfo = createTargetAsmInfo();
- return AsmInfo;
- }
+ const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
/// getSubtarget - This method returns a pointer to the specified type of
/// TargetSubtarget. In debug builds, it verifies that the object being
/// returned is of the correct type.
template<typename STC> const STC &getSubtarget() const {
- const TargetSubtarget *TST = getSubtargetImpl();
- assert(TST && dynamic_cast<const STC*>(TST) &&
- "Not the right kind of subtarget!");
- return *static_cast<const STC*>(TST);
+ return *static_cast<const STC*>(getSubtargetImpl());
}
/// getRegisterInfo - If register information is available, return it. If
/// not, return null. This is kept separate from RegInfo until RegInfo has
/// details of graph coloring register allocation removed from it.
///
- virtual const MRegisterInfo *getRegisterInfo() const { return 0; }
+ virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
+
+ /// getIntrinsicInfo - If intrinsic information is available, return it. If
+ /// not, return null.
+ ///
+ virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
/// getJITInfo - If this target supports a JIT, return information for it,
/// otherwise return null.
return InstrItineraryData();
}
+ /// getELFWriterInfo - If this target supports an ELF writer, return
+ /// information for it, otherwise return null.
+ ///
+ virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
+
+ /// hasMCRelaxAll - Check whether all machine code instructions should be
+ /// relaxed.
+ bool hasMCRelaxAll() const { return MCRelaxAll; }
+
+ /// setMCRelaxAll - Set whether all machine code instructions should be
+ /// relaxed.
+ void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
+
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
static Reloc::Model getRelocationModel();
/// setRelocationModel - Sets the code generation relocation model.
+ ///
static void setRelocationModel(Reloc::Model Model);
/// getCodeModel - Returns the code model. The choices are small, kernel,
static CodeModel::Model getCodeModel();
/// setCodeModel - Sets the code model.
+ ///
static void setCodeModel(CodeModel::Model Model);
+ /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
+ ///
+ static bool getAsmVerbosityDefault();
+
+ /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
+ /// is false.
+ static void setAsmVerbosityDefault(bool);
+
+ /// getDataSections - Return true if data objects should be emitted into their
+ /// own section, corresponds to -fdata-sections.
+ static bool getDataSections();
+
+ /// getFunctionSections - Return true if functions should be emitted into
+ /// their own section, corresponding to -ffunction-sections.
+ static bool getFunctionSections();
+
+ /// setDataSections - Set if the data are emit into separate sections.
+ static void setDataSections(bool);
+
+ /// setFunctionSections - Set if the functions are emit into separate
+ /// sections.
+ static void setFunctionSections(bool);
+
/// CodeGenFileType - These enums are meant to be passed into
- /// addPassesToEmitFile to indicate what type of file to emit.
+ /// addPassesToEmitFile to indicate what type of file to emit, and returned by
+ /// it to indicate what type of file could actually be made.
enum CodeGenFileType {
- AssemblyFile, ObjectFile, DynamicLibrary
+ CGFT_AssemblyFile,
+ CGFT_ObjectFile,
+ CGFT_Null // Do not emit any output.
};
- /// addPassesToEmitFile - Add passes to the specified pass manager to get
- /// the specified file emitted. Typically this will involve several steps of
- /// code generation. If Fast is set to true, the code generator should emit
- /// code as fast as possible, without regard for compile time. This method
- /// should return true if emission of this file type is not supported.
- ///
- virtual bool addPassesToEmitFile(FunctionPassManager &PM, std::ostream &Out,
- CodeGenFileType FileType, bool Fast) {
+ /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
+ /// on this target. User flag overrides.
+ virtual bool getEnableTailMergeDefault() const { return true; }
+
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of code
+ /// generation. This method should return true if emission of this file type
+ /// is not supported, or false on success.
+ virtual bool addPassesToEmitFile(PassManagerBase &,
+ formatted_raw_ostream &,
+ CodeGenFileType,
+ CodeGenOpt::Level,
+ bool = true) {
return true;
}
-
+
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// get machine code emitted. This uses a JITCodeEmitter object to handle
/// actually outputting the machine code and resolving things like the address
/// of functions. This method returns true if machine code emission is
/// not supported.
///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE, bool Fast) {
+ virtual bool addPassesToEmitMachineCode(PassManagerBase &,
+ JITCodeEmitter &,
+ CodeGenOpt::Level,
+ bool = true) {
return true;
}
-
- /// addPassesToEmitWholeFile - This method can be implemented by targets that
- /// require having the entire module at once. This is not recommended, do not
- /// use this.
- virtual bool WantsWholeFile() const { return false; }
- virtual bool addPassesToEmitWholeFile(PassManager &PM, std::ostream &Out,
- CodeGenFileType FileType, bool Fast) {
+ /// addPassesToEmitMC - Add passes to the specified pass manager to get
+ /// machine code emitted with the MCJIT. This method returns true if machine
+ /// code is not supported. It fills the MCContext Ctx pointer which can be
+ /// used to build custom MCStreamer.
+ ///
+ virtual bool addPassesToEmitMC(PassManagerBase &,
+ MCContext *&,
+ CodeGenOpt::Level,
+ bool = true) {
return true;
}
};
/// implemented with the LLVM target-independent code generator.
///
class LLVMTargetMachine : public TargetMachine {
+ std::string TargetTriple;
+
protected: // Can only create subclasses.
- LLVMTargetMachine() { }
-public:
+ LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
- /// addPassesToEmitFile - Add passes to the specified pass manager to get
- /// the specified file emitted. Typically this will involve several steps of
- /// code generation. If Fast is set to true, the code generator should emit
- /// code as fast as possible, without regard for compile time. This method
- /// should return true if emission of this file type is not supported.
- ///
- /// The default implementation of this method adds components from the
- /// LLVM retargetable code generator, invoking the methods below to get
- /// target-specific passes in standard locations.
+private:
+ /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
+ /// both emitting to assembly files or machine code output.
///
- virtual bool addPassesToEmitFile(FunctionPassManager &PM, std::ostream &Out,
- CodeGenFileType FileType, bool Fast);
+ bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+ bool DisableVerify, MCContext *&OutCtx);
+
+ virtual void setCodeModelForJIT();
+ virtual void setCodeModelForStatic();
+
+public:
+
+ /// addPassesToEmitFile - Add passes to the specified pass manager to get the
+ /// specified file emitted. Typically this will involve several steps of code
+ /// generation. If OptLevel is None, the code generator should emit code as
+ /// fast as possible, though the generated code may be less efficient.
+ virtual bool addPassesToEmitFile(PassManagerBase &PM,
+ formatted_raw_ostream &Out,
+ CodeGenFileType FileType,
+ CodeGenOpt::Level,
+ bool DisableVerify = true);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// get machine code emitted. This uses a JITCodeEmitter object to handle
/// actually outputting the machine code and resolving things like the address
/// of functions. This method returns true if machine code emission is
/// not supported.
///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE, bool Fast);
+ virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
+ JITCodeEmitter &MCE,
+ CodeGenOpt::Level,
+ bool DisableVerify = true);
+
+ /// addPassesToEmitMC - Add passes to the specified pass manager to get
+ /// machine code emitted with the MCJIT. This method returns true if machine
+ /// code is not supported. It fills the MCContext Ctx pointer which can be
+ /// used to build custom MCStreamer.
+ ///
+ virtual bool addPassesToEmitMC(PassManagerBase &PM,
+ MCContext *&Ctx,
+ CodeGenOpt::Level OptLevel,
+ bool DisableVerify = true);
/// Target-Independent Code Generator Pass Configuration Options.
/// addInstSelector - This method should add any "last minute" LLVM->LLVM
/// passes, then install an instruction selector pass, which converts from
/// LLVM code to machine instructions.
- virtual bool addInstSelector(FunctionPassManager &PM, bool Fast) {
+ virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
-
- /// addPostRegAllocPasses - This method may be implemented by targets that
- /// want to run passes after register allocation but before prolog-epilog
+
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
+ /// true if -print-machineinstrs should print after these passes.
+ virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+ /// addPostRegAlloc - This method may be implemented by targets that want
+ /// to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
- virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast) {
+ virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
+
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast) {
+ virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
- /// addAssemblyEmitter - This pass should be overridden by the target to add
- /// the asmprinter, if asm emission is supported. If this is not supported,
- /// 'true' should be returned.
- virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out) {
- return true;
- }
-
- /// addObjectWriter - This pass should be overridden by the target to add
- /// the object-file writer, if supported. If this is not supported,
- /// 'true' should be returned.
- virtual bool addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out) {
- return true;
- }
-
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned.
- virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
- MachineCodeEmitter &MCE) {
+ virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
+ JITCodeEmitter &) {
return true;
}
+
+ /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
+ /// on this target. User flag overrides.
+ virtual bool getEnableTailMergeDefault() const { return true; }
};
} // End llvm namespace
projects / oota-llvm.git / blobdiff