namespace llvm {
-class MachineInstr;
-class TargetMachine;
class TargetRegisterClass;
class LiveVariables;
class CalleeSavedInfo;
/// private, all access should go through the TargetOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
- LookupPtrRegClass = 1 << 0,
- Predicate = 1 << 1,
- OptionalDef = 1 << 2
+ LookupPtrRegClass = 0,
+ Predicate,
+ OptionalDef
};
}
/// isLookupPtrRegClass - Set if this operand is a pointer value and it
/// requires a callback to look up its register class.
- bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
+ bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
/// isPredicate - Set if this is one of the operands that made up of
- /// the predicate operand that controls an M_PREDICATED instruction.
- bool isPredicate() const { return Flags & TOI::Predicate; }
+ /// the predicate operand that controls an isPredicable() instruction.
+ bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
/// isOptionalDef - Set if this operand is a optional def.
///
- bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
+ bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
};
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
-const unsigned M_BRANCH_FLAG = 1 << 0;
-const unsigned M_CALL_FLAG = 1 << 1;
-const unsigned M_RET_FLAG = 1 << 2;
-const unsigned M_BARRIER_FLAG = 1 << 3;
-const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
-
-/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
-/// from memory. This should only be set on instructions that load a value from
-/// memory and return it in their only virtual register definition.
-const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
-
-/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
-/// modify memory. Instructions with this flag set are not necessarily simple
-/// store instructions, they may store a modified value based on their operands,
-/// or may not actually modify anything, for example.
-const unsigned M_MAY_STORE_FLAG = 1 << 6;
-
-const unsigned M_INDIRECT_FLAG = 1 << 7;
-const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
-
-// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
-// changed into a 3-address instruction if the first two operands cannot be
-// assigned to the same register. The target must implement the
-// TargetInstrInfo::convertToThreeAddress method for this instruction.
-const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
-
-// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
-// Z), which produces the same result if Y and Z are exchanged.
-const unsigned M_COMMUTABLE = 1 << 10;
-
-const unsigned M_TERMINATOR_FLAG = 1 << 11;
-
-// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
-// insertion support when the DAG scheduler is inserting it into a machine basic
-// block.
-const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
-
-const unsigned M_VARIADIC = 1 << 13;
-
-// M_PREDICABLE - Set if this instruction has a predicate operand that
-// controls execution. It may be set to 'always'.
-const unsigned M_PREDICABLE = 1 << 14;
-
-// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
-// at any time, e.g. constant generation, load from constant pool.
-const unsigned M_REMATERIALIZIBLE = 1 << 15;
-
-// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
-// (e.g. instructions with unique labels attached).
-const unsigned M_NOT_DUPLICABLE = 1 << 16;
-
-const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
-
-// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
-// are not captured by any operands of the instruction or other flags, and when
-// *all* instances of the instruction of that opcode have no side effects.
-//
-// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
-// both! If neither flag is set, then the instruction *always* has side effects.
-const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
-
-// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
-// side effects. The virtual method "isReallySideEffectFree" is called to
-// determine this. Load instructions are an example of where this is useful. In
-// general, loads always have side effects. However, loads from constant pools
-// don't. We let the specific back end make this determination.
-//
-// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
-// both! If neither flag is set, then the instruction *always* has side effects.
-const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
-
-
+/// TargetInstrDesc flags - These should be considered private to the
+/// implementation of the TargetInstrDesc class. Clients should use the
+/// predicate methods on TargetInstrDesc, not use these directly. These
+/// all correspond to bitfields in the TargetInstrDesc::Flags field.
+namespace TID {
+ enum {
+ Variadic = 0,
+ HasOptionalDef,
+ Return,
+ Call,
+ ImplicitDef,
+ Barrier,
+ Terminator,
+ Branch,
+ IndirectBranch,
+ Predicable,
+ NotDuplicable,
+ DelaySlot,
+ SimpleLoad,
+ MayStore,
+ NeverHasSideEffects,
+ MayHaveSideEffects,
+ Commutable,
+ ConvertibleTo3Addr,
+ UsesCustomDAGSchedInserter,
+ Rematerializable
+ };
+}
-class TargetInstrDescriptor {
+/// TargetInstrDesc - Describe properties that are true of each
+/// instruction in the target description file. This captures information about
+/// side effects, register use and many other things. There is one instance of
+/// this struct for each target instruction class, and the MachineInstr class
+/// points to this struct directly to describe itself.
+class TargetInstrDesc {
public:
unsigned short Opcode; // The opcode number.
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
- const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
+ const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
/// getOperandConstraint - Returns the value of the specific constraint if
/// it is set. Returns -1 if it is not set.
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
+ /// getOpcode - Return the opcode number for this descriptor.
+ unsigned getOpcode() const {
+ return Opcode;
+ }
+
/// getName - Return the name of the record in the .td file for this
/// instruction, for example "ADD8ri".
const char *getName() const {
/// operands but before the implicit definitions and uses (if any are
/// present).
bool isVariadic() const {
- return Flags & M_VARIADIC;
+ return Flags & (1 << TID::Variadic);
}
/// hasOptionalDef - Set if this instruction has an optional definition, e.g.
/// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef() const {
- return Flags & M_HAS_OPTIONAL_DEF;
+ return Flags & (1 << TID::HasOptionalDef);
}
/// getImplicitUses - Return a list of machine operands that are potentially
const unsigned *getImplicitDefs() const {
return ImplicitDefs;
}
+
+ /// getSchedClass - Return the scheduling class for this instruction. The
+ /// scheduling class is an index into the InstrItineraryData table. This
+ /// returns zero if there is no known scheduling information for the
+ /// instruction.
+ ///
+ unsigned getSchedClass() const {
+ return SchedClass;
+ }
bool isReturn() const {
- return Flags & M_RET_FLAG;
+ return Flags & (1 << TID::Return);
}
bool isCall() const {
- return Flags & M_CALL_FLAG;
+ return Flags & (1 << TID::Call);
}
/// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
/// which defines a register to an unspecified value. These basically
/// correspond to x = undef.
bool isImplicitDef() const {
- return Flags & M_IMPLICIT_DEF_FLAG;
+ return Flags & (1 << TID::ImplicitDef);
}
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.
bool isBarrier() const {
- return Flags & M_BARRIER_FLAG;
+ return Flags & (1 << TID::Barrier);
}
/// isTerminator - Returns true if this instruction part of the terminator for
/// Various passes use this to insert code into the bottom of a basic block,
/// but before control flow occurs.
bool isTerminator() const {
- return Flags & M_TERMINATOR_FLAG;
+ return Flags & (1 << TID::Terminator);
}
/// isBranch - Returns true if this is a conditional, unconditional, or
/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
/// get more information.
bool isBranch() const {
- return Flags & M_BRANCH_FLAG;
+ return Flags & (1 << TID::Branch);
}
/// isIndirectBranch - Return true if this is an indirect branch, such as a
/// branch through a register.
bool isIndirectBranch() const {
- return Flags & M_INDIRECT_FLAG;
+ return Flags & (1 << TID::IndirectBranch);
}
/// isConditionalBranch - Return true if this is a branch which may fall
return isBranch() & isBarrier() & !isIndirectBranch();
}
+ // isPredicable - Return true if this instruction has a predicate operand that
+ // controls execution. It may be set to 'always', or may be set to other
+ /// values. There are various methods in TargetInstrInfo that can be used to
+ /// control and modify the predicate in this instruction.
bool isPredicable() const {
- return Flags & M_PREDICABLE;
+ return Flags & (1 << TID::Predicable);
}
+ /// isNotDuplicable - Return true if this instruction cannot be safely
+ /// duplicated. For example, if the instruction has a unique labels attached
+ /// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable() const {
- return Flags & M_NOT_DUPLICABLE;
- }
-
- bool isCommutableInstr() const {
- return Flags & M_COMMUTABLE;
+ return Flags & (1 << TID::NotDuplicable);
}
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot() const {
- return Flags & M_DELAY_SLOT_FLAG;
- }
-
- /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
- /// custom insertion support when the DAG scheduler is inserting it into a
- /// machine basic block.
- bool usesCustomDAGSchedInsertionHook() const {
- return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
+ return Flags & (1 << TID::DelaySlot);
}
/// isSimpleLoad - Return true for instructions that are simple loads from
/// Instructions that return a value loaded from memory and then modified in
/// some way should not return true for this.
bool isSimpleLoad() const {
- return Flags & M_SIMPLE_LOAD_FLAG;
+ return Flags & (1 << TID::SimpleLoad);
}
+ //===--------------------------------------------------------------------===//
+ // Side Effect Analysis
+ //===--------------------------------------------------------------------===//
+
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore() const {
- return Flags & M_MAY_STORE_FLAG;
+ return Flags & (1 << TID::MayStore);
}
- unsigned getSchedClass() const {
- return SchedClass;
+ // TODO: mayLoad.
+
+ /// hasNoSideEffects - Return true if all instances of this instruction are
+ /// guaranteed to have no side effects other than:
+ /// 1. The register operands that are def/used by the MachineInstr.
+ /// 2. Registers that are implicitly def/used by the MachineInstr.
+ /// 3. Memory Accesses captured by mayLoad() or mayStore().
+ ///
+ /// Examples of other side effects would be calling a function, modifying
+ /// 'invisible' machine state like a control register, etc.
+ ///
+ /// If some instances of this instruction are side-effect free but others are
+ /// not, the hasConditionalSideEffects() property should return true, not this
+ /// one.
+ ///
+ /// Note that you should not call this method directly, instead, call the
+ /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
+ /// of the machine instruction.
+ bool hasNoSideEffects() const {
+ return Flags & (1 << TID::NeverHasSideEffects);
+ }
+
+ /// hasConditionalSideEffects - Return true if some instances of this
+ /// instruction are guaranteed to have no side effects other than those listed
+ /// for hasNoSideEffects(). To determine whether a specific machineinstr has
+ /// side effects, the TargetInstrInfo::isReallySideEffectFree virtual method
+ /// is invoked to decide.
+ ///
+ /// Note that you should not call this method directly, instead, call the
+ /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
+ /// of the machine instruction.
+ bool hasConditionalSideEffects() const {
+ return Flags & (1 << TID::MayHaveSideEffects);
+ }
+
+ //===--------------------------------------------------------------------===//
+ // Flags that indicate whether an instruction can be modified by a method.
+ //===--------------------------------------------------------------------===//
+
+ /// isCommutable - Return true if this may be a 2- or 3-address
+ /// instruction (of the form "X = op Y, Z, ..."), which produces the same
+ /// result if Y and Z are exchanged. If this flag is set, then the
+ /// TargetInstrInfo::commuteInstruction method may be used to hack on the
+ /// instruction.
+ ///
+ /// Note that this flag may be set on instructions that are only commutable
+ /// sometimes. In these cases, the call to commuteInstruction will fail.
+ /// Also note that some instructions require non-trivial modification to
+ /// commute them.
+ bool isCommutable() const {
+ return Flags & (1 << TID::Commutable);
+ }
+
+ /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
+ /// which can be changed into a 3-address instruction if needed. Doing this
+ /// transformation can be profitable in the register allocator, because it
+ /// means that the instruction can use a 2-address form if possible, but
+ /// degrade into a less efficient form if the source and dest register cannot
+ /// be assigned to the same register. For example, this allows the x86
+ /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
+ /// is the same speed as the shift but has bigger code size.
+ ///
+ /// If this returns true, then the target must implement the
+ /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
+ /// is allowed to fail if the transformation isn't valid for this specific
+ /// instruction (e.g. shl reg, 4 on x86).
+ ///
+ bool isConvertibleTo3Addr() const {
+ return Flags & (1 << TID::ConvertibleTo3Addr);
+ }
+
+ /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
+ /// custom insertion support when the DAG scheduler is inserting it into a
+ /// machine basic block. If this is true for the instruction, it basically
+ /// means that it is a pseudo instruction used at SelectionDAG time that is
+ /// expanded out into magic code by the target when MachineInstrs are formed.
+ ///
+ /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
+ /// is used to insert this into the MachineBasicBlock.
+ bool usesCustomDAGSchedInsertionHook() const {
+ return Flags & (1 << TID::UsesCustomDAGSchedInserter);
+ }
+
+ /// isRematerializable - Returns true if this instruction is a candidate for
+ /// remat. This flag is deprecated, please don't use it anymore. If this
+ /// flag is set, the isReallyTriviallyReMaterializable() method is called to
+ /// verify the instruction is really rematable.
+ bool isRematerializable() const {
+ return Flags & (1 << TID::Rematerializable);
}
};
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
- const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned NumOpcodes; // number of entries in the desc array
- unsigned numRealOpCodes; // number of non-dummy op codes
+ const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
+ unsigned NumOpcodes; // Number of entries in the desc array
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+ TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant opcodes: All instruction sets have these as their low opcodes.
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(unsigned Opcode) const {
- assert(Opcode < NumOpcodes);
- return desc[Opcode];
+ const TargetInstrDesc &get(unsigned Opcode) const {
+ assert(Opcode < NumOpcodes && "Invalid opcode!");
+ return Descriptors[Opcode];
}
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
bool isTriviallyReMaterializable(MachineInstr *MI) const {
- return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
+ return MI->getDesc().isRematerializable() &&
isReallyTriviallyReMaterializable(MI);
}
/// effects that are not captured by any operands of the instruction or other
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
- if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.hasNoSideEffects()) return false;
+ if (!TID.hasConditionalSideEffects()) return true;
return !isReallySideEffectFree(MI); // May have side effects
}
protected:
return false;
}
public:
- /// getOperandConstraint - Returns the value of the specific constraint if
- /// it is set. Returns -1 if it is not set.
- int getOperandConstraint(unsigned Opcode, unsigned OpNum,
- TOI::OperandConstraint Constraint) const {
- return get(Opcode).getOperandConstraint(OpNum, Constraint);
- }
-
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
/// libcodegen, not in libtarget.
class TargetInstrInfoImpl : public TargetInstrInfo {
protected:
- TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+ TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
: TargetInstrInfo(desc, NumOpcodes) {}
public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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