-//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
+//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file describes the target machine instructions to the code generator.
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
-#define LLVM_TARGET_MACHINEINSTRINFO_H
+#ifndef LLVM_TARGET_TARGETINSTRINFO_H
+#define LLVM_TARGET_TARGETINSTRINFO_H
-#include "Support/NonCopyable.h"
-#include "Support/DataTypes.h"
-#include <string>
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/Support/DataTypes.h"
#include <vector>
+#include <cassert>
+
+namespace llvm {
-class MachineInstrDescriptor;
-class TmpInstruction;
class MachineInstr;
class TargetMachine;
class Value;
+class Type;
class Instruction;
-class Method;
+class Constant;
+class Function;
+class MachineCodeForInstruction;
//---------------------------------------------------------------------------
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
-typedef int MachineOpCode;
-typedef int OpCodeMask;
-typedef int InstrSchedClass;
-
-// Global variable holding an array of descriptors for machine instructions.
-// The actual object needs to be created separately for each target machine.
-// This variable is initialized and reset by class MachineInstrInfo.
-//
-// FIXME: This should be a property of the target so that more than one target
-// at a time can be active...
-//
-extern const MachineInstrDescriptor *TargetInstrDescriptors;
-
+typedef short MachineOpCode;
+typedef unsigned InstrSchedClass;
//---------------------------------------------------------------------------
-// struct MachineInstrDescriptor:
+// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
-//
-// class MachineInstructionInfo
-// Interface to description of machine instructions
-//
-//---------------------------------------------------------------------------
-
-
-const unsigned int M_NOP_FLAG = 1;
-const unsigned int M_BRANCH_FLAG = 1 << 1;
-const unsigned int M_CALL_FLAG = 1 << 2;
-const unsigned int M_RET_FLAG = 1 << 3;
-const unsigned int M_ARITH_FLAG = 1 << 4;
-const unsigned int M_CC_FLAG = 1 << 6;
-const unsigned int M_LOGICAL_FLAG = 1 << 6;
-const unsigned int M_INT_FLAG = 1 << 7;
-const unsigned int M_FLOAT_FLAG = 1 << 8;
-const unsigned int M_CONDL_FLAG = 1 << 9;
-const unsigned int M_LOAD_FLAG = 1 << 10;
-const unsigned int M_PREFETCH_FLAG = 1 << 11;
-const unsigned int M_STORE_FLAG = 1 << 12;
-const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
-const unsigned int M_PSEUDO_FLAG = 1 << 14;
-
+//
-struct MachineInstrDescriptor {
- std::string opCodeString; // Assembly language mnemonic for the opcode.
- int numOperands; // Number of args; -1 if variable #args
- int resultPos; // Position of the result; -1 if no result
- unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
+const unsigned M_NOP_FLAG = 1 << 0;
+const unsigned M_BRANCH_FLAG = 1 << 1;
+const unsigned M_CALL_FLAG = 1 << 2;
+const unsigned M_RET_FLAG = 1 << 3;
+const unsigned M_BARRIER_FLAG = 1 << 4;
+const unsigned M_CC_FLAG = 1 << 6;
+const unsigned M_LOAD_FLAG = 1 << 10;
+const unsigned M_STORE_FLAG = 1 << 12;
+// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
+const unsigned M_2_ADDR_FLAG = 1 << 15;
+
+// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
+// block? Typically this is things like return and branch instructions.
+// Various passes use this to insert code into the bottom of a basic block, but
+// before control flow occurs.
+const unsigned M_TERMINATOR_FLAG = 1 << 16;
+
+struct TargetInstrDescriptor {
+ const char * Name; // Assembly language mnemonic for the opcode.
+ int numOperands; // Number of args; -1 if variable #args
+ int resultPos; // Position of the result; -1 if no result
+ unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
- // smallest -ve value is -(maxImmedConst+1).
- unsigned int numDelaySlots; // Number of delay slots after instruction
- unsigned int latency; // Latency in machine cycles
- InstrSchedClass schedClass; // enum identifying instr sched class
- unsigned int iclass; // flags identifying machine instr class
+ // smallest -ve value is -(maxImmedConst+1).
+ unsigned numDelaySlots; // Number of delay slots after instruction
+ unsigned latency; // Latency in machine cycles
+ InstrSchedClass schedClass; // enum identifying instr sched class
+ unsigned Flags; // flags identifying machine instr class
+ unsigned TSFlags; // Target Specific Flag values
+ const unsigned *ImplicitUses; // Registers implicitly read by this instr
+ const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
};
-class MachineInstrInfo : public NonCopyableV {
-public:
- const TargetMachine& target;
-
-protected:
- const MachineInstrDescriptor* desc; // raw array to allow static init'n
- unsigned int descSize; // number of entries in the desc array
- unsigned int numRealOpCodes; // number of non-dummy op codes
+//---------------------------------------------------------------------------
+///
+/// TargetInstrInfo - Interface to description of machine instructions
+///
+class TargetInstrInfo {
+ const TargetInstrDescriptor* desc; // raw array to allow static init'n
+ unsigned NumOpcodes; // number of entries in the desc array
+ unsigned numRealOpCodes; // number of non-dummy op codes
+ TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
+ void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- MachineInstrInfo(const TargetMachine& tgt,
- const MachineInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
- virtual ~MachineInstrInfo();
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+ virtual ~TargetInstrInfo();
+
+ // Invariant: All instruction sets use opcode #0 as the PHI instruction
+ enum { PHI = 0 };
- unsigned getNumRealOpCodes() const { return numRealOpCodes; }
- unsigned getNumTotalOpCodes() const { return descSize; }
+ unsigned getNumOpcodes() const { return NumOpcodes; }
- const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
- assert(opCode >= 0 && opCode < (int)descSize);
- return desc[opCode];
+ /// get - Return the machine instruction descriptor that corresponds to the
+ /// specified instruction opcode.
+ ///
+ const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
+ assert((unsigned)Opcode < NumOpcodes);
+ return desc[Opcode];
}
-
- int getNumOperands(MachineOpCode opCode) const {
- return getDescriptor(opCode).numOperands;
+
+ const char *getName(MachineOpCode Opcode) const {
+ return get(Opcode).Name;
}
- int getResultPos(MachineOpCode opCode) const {
- return getDescriptor(opCode).resultPos;
+ int getNumOperands(MachineOpCode Opcode) const {
+ return get(Opcode).numOperands;
}
-
- unsigned getNumDelaySlots(MachineOpCode opCode) const {
- return getDescriptor(opCode).numDelaySlots;
+
+
+ InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
+ return get(Opcode).schedClass;
}
-
- InstrSchedClass getSchedClass(MachineOpCode opCode) const {
- return getDescriptor(opCode).schedClass;
+
+ const unsigned *getImplicitUses(MachineOpCode Opcode) const {
+ return get(Opcode).ImplicitUses;
}
-
+
+ const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
+ return get(Opcode).ImplicitDefs;
+ }
+
+
//
// Query instruction class flags according to the machine-independent
// flags listed above.
//
- unsigned int getIClass(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass;
- }
- bool isNop(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_NOP_FLAG;
- }
- bool isBranch(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
- }
- bool isCall(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_CALL_FLAG;
- }
- bool isReturn(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_RET_FLAG;
- }
- bool isControlFlow(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_BRANCH_FLAG
- || getDescriptor(opCode).iclass & M_CALL_FLAG
- || getDescriptor(opCode).iclass & M_RET_FLAG;
+ bool isReturn(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_RET_FLAG;
}
- bool isArith(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_RET_FLAG;
- }
- bool isCCInstr(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_CC_FLAG;
+
+ bool isTwoAddrInstr(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_2_ADDR_FLAG;
}
- bool isLogical(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
+ bool isTerminatorInstr(unsigned Opcode) const {
+ return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
- bool isIntInstr(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_INT_FLAG;
+
+ /// Return true if the instruction is a register to register move
+ /// and leave the source and dest operands in the passed parameters.
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ return false;
}
- bool isFloatInstr(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
+
+ /// Insert a goto (unconditional branch) sequence to TMBB, at the
+ /// end of MBB
+ virtual void insertGoto(MachineBasicBlock& MBB,
+ MachineBasicBlock& TMBB) const {
+ assert(0 && "Target didn't implement insertGoto!");
}
- bool isConditional(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_CONDL_FLAG;
+
+ /// Reverses the branch condition of the MachineInstr pointed by
+ /// MI. The instruction is replaced and the new MI is returned.
+ virtual MachineBasicBlock::iterator
+ reverseBranchCondition(MachineBasicBlock::iterator MI) const {
+ assert(0 && "Target didn't implement reverseBranchCondition!");
+ abort();
+ return MI;
}
- bool isLoad(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_LOAD_FLAG;
+
+ //-------------------------------------------------------------------------
+ // Code generation support for creating individual machine instructions
+ //
+ // WARNING: These methods are Sparc specific
+ //
+ // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
+ //
+ //-------------------------------------------------------------------------
+
+ unsigned getNumDelaySlots(MachineOpCode Opcode) const {
+ return get(Opcode).numDelaySlots;
}
- bool isPrefetch(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
+ bool isCCInstr(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_CC_FLAG;
}
- bool isLoadOrPrefetch(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_LOAD_FLAG
- || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
+ bool isNop(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_NOP_FLAG;
}
- bool isStore(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_STORE_FLAG;
+ bool isBranch(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_BRANCH_FLAG;
}
- bool isMemoryAccess(MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_LOAD_FLAG
- || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
- || getDescriptor(opCode).iclass & M_STORE_FLAG;
+ /// isBarrier - Returns true if the specified instruction stops control flow
+ /// from executing the instruction immediately following it. Examples include
+ /// unconditional branches and return instructions.
+ bool isBarrier(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_BARRIER_FLAG;
}
- bool isDummyPhiInstr(const MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
+ bool isCall(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_CALL_FLAG;
}
-
-
- // delete this later *******
- bool isPhi(const MachineOpCode opCode) const
- { return isDummyPhiInstr(opCode); }
-
- bool isPseudoInstr(const MachineOpCode opCode) const {
- return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
+ bool isLoad(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_LOAD_FLAG;
}
-
-
- // Check if an instruction can be issued before its operands are ready,
- // or if a subsequent instruction that uses its result can be issued
- // before the results are ready.
- // Default to true since most instructions on many architectures allow this.
- //
- virtual bool hasOperandInterlock(MachineOpCode opCode) const {
- return true;
+ bool isStore(MachineOpCode Opcode) const {
+ return get(Opcode).Flags & M_STORE_FLAG;
}
-
- virtual bool hasResultInterlock(MachineOpCode opCode) const {
+ virtual bool hasResultInterlock(MachineOpCode Opcode) const {
return true;
}
-
+
//
// Latencies for individual instructions and instruction pairs
//
- virtual int minLatency(MachineOpCode opCode) const {
- return getDescriptor(opCode).latency;
+ virtual int minLatency(MachineOpCode Opcode) const {
+ return get(Opcode).latency;
}
- virtual int maxLatency(MachineOpCode opCode) const {
- return getDescriptor(opCode).latency;
+ virtual int maxLatency(MachineOpCode Opcode) const {
+ return get(Opcode).latency;
}
//
// Which operand holds an immediate constant? Returns -1 if none
//
- virtual int getImmmedConstantPos(MachineOpCode opCode) const {
+ virtual int getImmedConstantPos(MachineOpCode Opcode) const {
return -1; // immediate position is machine specific, so say -1 == "none"
}
// Check if the specified constant fits in the immediate field
// of this machine instruction
//
- virtual bool constantFitsInImmedField(MachineOpCode opCode,
+ virtual bool constantFitsInImmedField(MachineOpCode Opcode,
int64_t intValue) const;
- // Return the largest +ve constant that can be held in the IMMMED field
+ // Return the largest positive constant that can be held in the IMMED field
// of this machine instruction.
// isSignExtended is set to true if the value is sign-extended before use
// (this is true for all immediate fields in SPARC instructions).
// Return 0 if the instruction has no IMMED field.
//
- virtual uint64_t maxImmedConstant(MachineOpCode opCode,
+ virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
bool &isSignExtended) const {
- isSignExtended = getDescriptor(opCode).immedIsSignExtended;
- return getDescriptor(opCode).maxImmedConst;
+ isSignExtended = get(Opcode).immedIsSignExtended;
+ return get(Opcode).maxImmedConst;
}
-
- //-------------------------------------------------------------------------
- // Code generation support for creating individual machine instructions
- //-------------------------------------------------------------------------
-
- // Create an instruction sequence to put the constant `val' into
- // the virtual register `dest'. `val' may be a Constant or a
- // GlobalValue, viz., the constant address of a global variable or function.
- // The generated instructions are returned in `minstrVec'.
- // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
- //
- virtual void CreateCodeToLoadConst(Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& minstrVec,
- std::vector<TmpInstruction*> &) const = 0;
-
- // Create an instruction sequence to copy an integer value `val'
- // to a floating point value `dest' by copying to memory and back.
- // val must be an integral type. dest must be a Float or Double.
- // The generated instructions are returned in `minstrVec'.
- // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
- //
- virtual void CreateCodeToCopyIntToFloat(Method* method,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& minstVec,
- std::vector<TmpInstruction*>& tmpVec,
- TargetMachine& target) const = 0;
-
- // Similarly, create an instruction sequence to copy an FP value
- // `val' to an integer value `dest' by copying to memory and back.
- // See the previous function for information about return values.
- //
- virtual void CreateCodeToCopyFloatToInt(Method* method,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& minstVec,
- std::vector<TmpInstruction*>& tmpVec,
- TargetMachine& target) const = 0;
-
-
- // create copy instruction(s)
- virtual void
- CreateCopyInstructionsByType(const TargetMachine& target,
- Value* src,
- Instruction* dest,
- std::vector<MachineInstr*>& minstrVec) const = 0;
};
+} // End llvm namespace
+
#endif
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