Remove. Not needed.

[oota-llvm.git] / include / llvm / Target / TargetInstrInfo.h

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 210f3b1f8a2e425f64dccc70349238ac3c3ccf06..00a05569b95d8ff0478d4dcbc67d84b80e21816f 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -24,11 +24,6 @@ namespace llvm {
 
 class MachineInstr;
 class TargetMachine;
-class Value;
-class Type;
-class Instruction;
-class Constant;
-class Function;
 class MachineCodeForInstruction;
 class TargetRegisterClass;
 class LiveVariables;
@@ -79,9 +74,13 @@ const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
 // operands in addition to the minimum number operands specified.
 const unsigned M_VARIABLE_OPS = 1 << 11;
 
-// M_PREDICATED - Set if this instruction has a predicate that controls its
-// execution.
-const unsigned M_PREDICATED = 1 << 12;
+// M_PREDICABLE - Set if this instruction has a predicate operand that
+// controls execution. It may be set to 'always'.
+const unsigned M_PREDICABLE = 1 << 12;
+
+// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
+// at any time, e.g. constant generation, load from constant pool.
+const unsigned M_REMATERIALIZIBLE = 1 << 13;
 
 
 // Machine operand flags
@@ -89,8 +88,8 @@ const unsigned M_PREDICATED = 1 << 12;
 // requires a callback to look up its register class.
 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
 
-/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
-/// operand that controls an M_PREDICATED instruction.
+/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
+/// predicate operand that controls an M_PREDICATED instruction.
 const unsigned M_PREDICATE_OPERAND = 1 << 1;
 
 namespace TOI {
@@ -132,13 +131,19 @@ public:
   /// it is set. Returns -1 if it is not set.
   int getOperandConstraint(unsigned OpNum,
                            TOI::OperandConstraint Constraint) const {
-    assert(OpNum < numOperands && "Invalid operand # of TargetInstrInfo");
-    if (OpInfo[OpNum].Constraints & (1 << Constraint)) {
+    assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+           "Invalid operand # of TargetInstrInfo");
+    if (OpNum < numOperands &&
+        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
       unsigned Pos = 16 + Constraint * 4;
       return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
     }
     return -1;
   }
+
+  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
+  /// dest operand. Returns -1 if there isn't one.
+  int findTiedToSrcOperand(unsigned OpNum) const;
 };
 
 
@@ -160,7 +165,8 @@ public:
   // Invariant opcodes: All instruction sets have these as their low opcodes.
   enum { 
     PHI = 0,
-    INLINEASM = 1
+    INLINEASM = 1,
+    LABEL = 2
   };
 
   unsigned getNumOpcodes() const { return NumOpcodes; }
@@ -202,8 +208,11 @@ public:
     return get(Opcode).Flags & M_RET_FLAG;
   }
 
-  bool isPredicated(MachineOpCode Opcode) const {
-    return get(Opcode).Flags & M_PREDICATED;
+  bool isPredicable(MachineOpCode Opcode) const {
+    return get(Opcode).Flags & M_PREDICABLE;
+  }
+  bool isReMaterializable(MachineOpCode Opcode) const {
+    return get(Opcode).Flags & M_REMATERIALIZIBLE;
   }
   bool isCommutableInstr(MachineOpCode Opcode) const {
     return get(Opcode).Flags & M_COMMUTABLE;
@@ -257,17 +266,6 @@ public:
     return get(Opcode).getOperandConstraint(OpNum, Constraint);
   }
 
-  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
-  /// dest operand. Returns -1 if there isn't one.
-  int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
-
-  /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
-  /// instruction if it has one.  This is used by codegen passes that update
-  /// DWARF line number info as they modify the code.
-  virtual unsigned getDWARF_LABELOpcode() const {
-    return 0;
-  }
-  
   /// Return true if the instruction is a register to register move
   /// and leave the source and dest operands in the passed parameters.
   virtual bool isMoveInstr(const MachineInstr& MI,
@@ -331,10 +329,16 @@ public:
   ///    just return false, leaving TBB/FBB null.
   /// 2. If this block ends with only an unconditional branch, it sets TBB to be
   ///    the destination block.
-  /// 3. If this block ends with an conditional branch, it returns the 'true'
-  ///    destination in TBB, the 'false' destination in FBB, and a list of
-  ///    operands that evaluate the condition.  These operands can be passed to
-  ///    other TargetInstrInfo methods to create new branches.
+  /// 3. If this block ends with an conditional branch and it falls through to
+  ///    an successor block, it sets TBB to be the branch destination block and a
+  ///    list of operands that evaluate the condition. These
+  ///    operands can be passed to other TargetInstrInfo methods to create new
+  ///    branches.
+  /// 4. If this block ends with an conditional branch and an unconditional
+  ///    block, it returns the 'true' destination in TBB, the 'false' destination
+  ///    in FBB, and a list of operands that evaluate the condition. These
+  ///    operands can be passed to other TargetInstrInfo methods to create new
+  ///    branches.
   ///
   /// Note that RemoveBranch and InsertBranch must be implemented to support
   /// cases where this method returns success.
@@ -385,11 +389,17 @@ public:
     abort();
   }
 
+  /// PredicateInstruction - Convert the instruction into a predicated
+  /// instruction. It returns true if the operation was successful.
+  virtual bool PredicateInstruction(MachineInstr *MI,
+                                    std::vector<MachineOperand> &Cond) const;
+
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
   /// values.
   virtual const TargetRegisterClass *getPointerRegClass() const {
     assert(0 && "Target didn't implement getPointerRegClass!");
     abort();
+    return 0; // Must return a value in order to compile with VS 2005
   }
 };