Add support to tablegen for specifying subregister classes on a per register class...

[oota-llvm.git] / include / llvm / Target / MRegisterInfo.h

diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 723ab69bd13fe6560ba9244ab6b5b1a4979ca7e9..ea10c1cc47bfb91d87102a8dba73c225adca1ff9 100644 (file)
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -64,6 +64,7 @@ private:
   const vt_iterator VTs;
   const sc_iterator SubClasses;
   const sc_iterator SuperClasses;
+  const sc_iterator SubRegClasses;
   const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
   const iterator RegsBegin, RegsEnd;
 public:
@@ -71,8 +72,10 @@ public:
                       const MVT::ValueType *vts,
                       const TargetRegisterClass * const *subcs,
                       const TargetRegisterClass * const *supcs,
+                      const TargetRegisterClass * const *subregcs,
                       unsigned RS, unsigned Al, iterator RB, iterator RE)
     : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+    SubRegClasses(subregcs),
     RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
   virtual ~TargetRegisterClass() {}     // Allow subclasses
   
@@ -167,6 +170,47 @@ public:
     return I;
   }
   
+  /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
+  /// class of a sub-register class for this TargetRegisterClass.
+  bool hasSubRegForClass(const TargetRegisterClass *cs) const {
+    for (int i = 0; SubRegClasses[i] != NULL; ++i) 
+      if (SubRegClasses[i] == cs)
+        return true;
+    return false;
+  }
+
+  /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
+  /// class of a sub-register class for this TargetRegisterClass.
+  bool hasClassForSubReg(unsigned SubReg) const {
+    --SubReg;
+    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
+      if (i == SubReg)
+        return true;
+    return false;
+  }
+
+  /// getClassForSubReg - return theTargetRegisterClass for the sub-register
+  /// at idx for this TargetRegisterClass.
+  sc_iterator getClassForSubReg(unsigned SubReg) const {
+    --SubReg;
+    for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 
+      if (i == SubReg)
+        return &SubRegClasses[i];
+    return NULL;
+  }
+  
+  /// subregclasses_begin / subregclasses_end - Loop over all of
+  /// the subregister classes of this register class.
+  sc_iterator subregclasses_begin() const {
+    return SubRegClasses;
+  }
+  
+  sc_iterator subregclasses_end() const {
+    sc_iterator I = SubRegClasses;
+    while (*I != NULL) ++I;
+    return I;
+  }
+  
   /// allocation_order_begin/end - These methods define a range of registers
   /// which specify the registers in this class that are valid to register
   /// allocate, and the preferred order to allocate them in.  For example,