#define LLVM_TARGET_MREGISTERINFO_H
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/ValueTypes.h"
#include <cassert>
#include <functional>
class Type;
class MachineFunction;
class MachineInstr;
+class MachineLocation;
+class MachineMove;
class TargetRegisterClass;
-/// MRegisterDesc - This record contains all of the information known about a
-/// particular register. The AliasSet field (if not null) contains a pointer to
-/// a Zero terminated array of registers that this register aliases. This is
+/// TargetRegisterDesc - This record contains all of the information known about
+/// a particular register. The AliasSet field (if not null) contains a pointer
+/// to a Zero terminated array of registers that this register aliases. This is
/// needed for architectures like X86 which have AL alias AX alias EAX.
/// Registers that this does not apply to simply should set this to null.
///
-struct MRegisterDesc {
+struct TargetRegisterDesc {
const char *Name; // Assembly language name for the register
const unsigned *AliasSet; // Register Alias Set, described above
};
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
+ typedef const MVT::ValueType* vt_iterator;
+ typedef const TargetRegisterClass* const * sc_iterator;
private:
+ unsigned ID;
+ bool isSubClass;
+ const vt_iterator VTs;
+ const sc_iterator SubClasses;
+ const sc_iterator SuperClasses;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
- : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
+ TargetRegisterClass(unsigned id,
+ const MVT::ValueType *vts,
+ const TargetRegisterClass * const *subcs,
+ const TargetRegisterClass * const *supcs,
+ unsigned RS, unsigned Al, iterator RB, iterator RE)
+ : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+ RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
-
- // begin/end - Return all of the registers in this class.
+
+ /// getID() - Return the register class ID number.
+ ///
+ unsigned getID() const { return ID; }
+
+ /// begin/end - Return all of the registers in this class.
+ ///
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
- // getNumRegs - Return the number of registers in this class
+ /// getNumRegs - Return the number of registers in this class.
+ ///
unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
- // getRegister - Return the specified register in the class
+ /// getRegister - Return the specified register in the class.
+ ///
unsigned getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register number out of range!");
return RegsBegin[i];
return false;
}
+ /// hasType - return true if this TargetRegisterClass has the ValueType vt.
+ ///
+ bool hasType(MVT::ValueType vt) const {
+ for(int i = 0; VTs[i] != MVT::Other; ++i)
+ if (VTs[i] == vt)
+ return true;
+ return false;
+ }
+
+ /// vt_begin / vt_end - Loop over all of the value types that can be
+ /// represented by values in this register class.
+ vt_iterator vt_begin() const {
+ return VTs;
+ }
+
+ vt_iterator vt_end() const {
+ vt_iterator I = VTs;
+ while (*I != MVT::Other) ++I;
+ return I;
+ }
+
+ /// hasSubRegClass - return true if the specified TargetRegisterClass is a
+ /// sub-register class of this TargetRegisterClass.
+ bool hasSubRegClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SubClasses[i] != NULL; ++i)
+ if (SubClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
+ /// this register class.
+ sc_iterator subclasses_begin() const {
+ return SubClasses;
+ }
+
+ sc_iterator subclasses_end() const {
+ sc_iterator I = SubClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
+ /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
+ /// super-register class of this TargetRegisterClass.
+ bool hasSuperRegClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SuperClasses[i] != NULL; ++i)
+ if (SuperClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// superclasses_begin / superclasses_end - Loop over all of the super-classes
+ /// of this register class.
+ sc_iterator superclasses_begin() const {
+ return SuperClasses;
+ }
+
+ sc_iterator superclasses_end() const {
+ sc_iterator I = SuperClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
///
/// By default, these methods return all registers in the class.
///
- virtual iterator allocation_order_begin(MachineFunction &MF) const {
+ virtual iterator allocation_order_begin(const MachineFunction &MF) const {
return begin();
}
- virtual iterator allocation_order_end(MachineFunction &MF) const {
+ virtual iterator allocation_order_end(const MachineFunction &MF) const {
return end();
}
/// MRegisterInfo base class - We assume that the target defines a static array
-/// of MRegisterDesc objects that represent all of the machine registers that
-/// the target has. As such, we simply have to track a pointer to this array so
-/// that we can turn register number into a register descriptor.
+/// of TargetRegisterDesc objects that represent all of the machine registers
+/// that the target has. As such, we simply have to track a pointer to this
+/// array so that we can turn register number into a register descriptor.
///
class MRegisterInfo {
public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
- const MRegisterDesc *Desc; // Pointer to the descriptor array
+ const TargetRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
protected:
- MRegisterInfo(const MRegisterDesc *D, unsigned NR,
+ MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
virtual ~MRegisterInfo();
public:
enum { // Define some target independent constants
- /// NoRegister - This 'hard' register is a 'noop' register for all backends.
- /// This is used as the destination register for instructions that do not
- /// produce a value. Some frontends may use this as an operand register to
- /// mean special things, for example, the Sparc backend uses R0 to mean %g0
- /// which always PRODUCES the value 0. The X86 backend does not use this
- /// value as an operand register, except for memory references.
- ///
+ /// NoRegister - This physical register is not a real target register. It
+ /// is useful as a sentinal.
NoRegister = 0,
/// FirstVirtualRegister - This is the first register number that is
/// considered to be a 'virtual' register, which is part of the SSA
/// namespace. This must be the same for all targets, which means that each
/// target is limited to 1024 registers.
- ///
- FirstVirtualRegister = 1024,
+ FirstVirtualRegister = 1024
};
/// isPhysicalRegister - Return true if the specified register number is in
/// indicating if a register is allocatable or not.
std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
- const MRegisterDesc &operator[](unsigned RegNo) const {
+ const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
return Desc[RegNo];
/// Provide a get method, equivalent to [], but more useful if we have a
/// pointer to this object.
///
- const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
+ const TargetRegisterDesc &get(unsigned RegNo) const {
+ return operator[](RegNo);
+ }
/// getAliasSet - Return the set of registers aliased by the specified
/// register, or a null list of there are none. The list returned is zero
unsigned getNumRegClasses() const {
return regclass_end()-regclass_begin();
}
+
+ /// getRegClass - Returns the register class associated with the enumeration
+ /// value. See class TargetOperandInfo.
+ const TargetRegisterClass *getRegClass(unsigned i) const {
+ assert(i <= getNumRegClasses() && "Register Class ID out of range");
+ return i ? RegClassBegin[i - 1] : NULL;
+ }
//===--------------------------------------------------------------------===//
// Interfaces used by the register allocator and stack frame
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const = 0;
- /// isLoadFromStackSlot - If the specified machine instruction is a direct
- /// load from a stack slot, return the virtual or physical register number of
- /// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return false if the instruction has
- /// any side effects other than loading from the stack slot.
- virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
- return 0;
- }
-
/// foldMemoryOperand - Attempt to fold a load or store of the
/// specified stack slot into the specified machine instruction for
/// the specified operand. If this is possible, a new instruction
virtual void emitPrologue(MachineFunction &MF) const = 0;
virtual void emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const = 0;
+
+ //===--------------------------------------------------------------------===//
+ /// Debug information queries.
+
+ /// getDwarfRegNum - Map a target register to an equivalent dwarf register
+ /// number. Returns -1 if there is no equivalent value.
+ virtual int getDwarfRegNum(unsigned RegNum) const = 0;
+
+ /// getFrameRegister - This method should return the register used as a base
+ /// for values allocated in the current stack frame.
+ virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
+
+ /// getRARegister - This method should return the register where the return
+ /// address can be found.
+ virtual unsigned getRARegister() const = 0;
+
+ /// getLocation - This method should return the actual location of a frame
+ /// variable given the frame index. The location is returned in ML.
+ /// Subclasses should override this method for special handling of frame
+ /// variables and call MRegisterInfo::getLocation for the default action.
+ virtual void getLocation(MachineFunction &MF, unsigned Index,
+ MachineLocation &ML) const;
+
+ /// getInitialFrameState - Returns a list of machine moves that are assumed
+ /// on entry to all functions. Note that LabelID is ignored (assumed to be
+ /// the beginning of the function.)
+ virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
};
// This is useful when building DenseMaps keyed on virtual registers
projects / oota-llvm.git / blobdiff