LC_DYLIB_CODE_SIGN_DRS = 0x0000002Bu,
LC_ENCRYPTION_INFO_64 = 0x0000002Cu,
LC_LINKER_OPTION = 0x0000002Du,
- LC_LINKER_OPTIMIZATION_HINT = 0x0000002Eu
+ LC_LINKER_OPTIMIZATION_HINT = 0x0000002Eu,
+ LC_VERSION_MIN_TVOS = 0x0000002Fu,
+ LC_VERSION_MIN_WATCHOS = 0x00000030u,
};
enum : uint32_t {
SG_NORELOC = 0x4u,
SG_PROTECTED_VERSION_1 = 0x8u,
-
// Constant masks for the "flags" field in llvm::MachO::section and
// llvm::MachO::section_64
SECTION_TYPE = 0x000000ffu, // SECTION_TYPE
EXPORT_SYMBOL_FLAGS_KIND_ABSOLUTE = 0x02u
};
-
enum {
// Constant masks for the "n_type" field in llvm::MachO::nlist and
// llvm::MachO::nlist_64
SELF_LIBRARY_ORDINAL = 0x0,
MAX_LIBRARY_ORDINAL = 0xfd,
DYNAMIC_LOOKUP_ORDINAL = 0xfe,
- EXECUTABLE_ORDINAL = 0xff
+ EXECUTABLE_ORDINAL = 0xff
};
enum StabType {
// Must be followed by ARM64_RELOC_PAGE21 or ARM64_RELOC_PAGEOFF12.
ARM64_RELOC_ADDEND = 10,
-
// Constant values for the r_type field in an x86_64 architecture
// llvm::MachO::relocation_info or llvm::MachO::scattered_relocation_info
// structure
VM_PROT_EXECUTE = 0x4
};
-
// Structs from <mach-o/loader.h>
struct mach_header {
flags:8;
};
-
struct twolevel_hints_command {
uint32_t cmd;
uint32_t cmdsize;
uint64_t stacksize;
};
-
// Structs from <mach-o/fat.h>
struct fat_header {
uint32_t magic;
uint64_t n_value;
};
-
// Byte order swapping functions for MachO structs
inline void swapStruct(mach_header &mh) {
char mmst_rsrv[6];
};
- struct xmm_reg {
+ struct xmm_reg_t {
char xmm_reg[16];
};
mmst_reg_t fpu_stmm5;
mmst_reg_t fpu_stmm6;
mmst_reg_t fpu_stmm7;
- xmm_reg fpu_xmm0;
- xmm_reg fpu_xmm1;
- xmm_reg fpu_xmm2;
- xmm_reg fpu_xmm3;
- xmm_reg fpu_xmm4;
- xmm_reg fpu_xmm5;
- xmm_reg fpu_xmm6;
- xmm_reg fpu_xmm7;
- xmm_reg fpu_xmm8;
- xmm_reg fpu_xmm9;
- xmm_reg fpu_xmm10;
- xmm_reg fpu_xmm11;
- xmm_reg fpu_xmm12;
- xmm_reg fpu_xmm13;
- xmm_reg fpu_xmm14;
- xmm_reg fpu_xmm15;
+ xmm_reg_t fpu_xmm0;
+ xmm_reg_t fpu_xmm1;
+ xmm_reg_t fpu_xmm2;
+ xmm_reg_t fpu_xmm3;
+ xmm_reg_t fpu_xmm4;
+ xmm_reg_t fpu_xmm5;
+ xmm_reg_t fpu_xmm6;
+ xmm_reg_t fpu_xmm7;
+ xmm_reg_t fpu_xmm8;
+ xmm_reg_t fpu_xmm9;
+ xmm_reg_t fpu_xmm10;
+ xmm_reg_t fpu_xmm11;
+ xmm_reg_t fpu_xmm12;
+ xmm_reg_t fpu_xmm13;
+ xmm_reg_t fpu_xmm14;
+ xmm_reg_t fpu_xmm15;
char fpu_rsrv4[6*16];
uint32_t fpu_reserved1;
};