//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_MC_MCSCHEDMODEL_H
-#define LLVM_MC_MCSCHEDMODEL_H
+#ifndef LLVM_MC_MCSCHEDULE_H
+#define LLVM_MC_MCSCHEDULE_H
#include "llvm/Support/DataTypes.h"
#include <cassert>
#ifndef NDEBUG
const char *Name;
#endif
- unsigned Count; // Number of resource of this kind
+ unsigned NumUnits; // Number of resource of this kind
unsigned SuperIdx; // Index of the resources kind that contains this kind.
+ // Number of resources that may be buffered.
+ //
+ // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
+ // cycle after dispatch. This should be used for out-of-order cpus when
+ // instructions that use this resource can be buffered in a reservaton
+ // station.
+ //
+ // Unbuffered resources (BufferSize == 0) always consume their resource some
+ // fixed number of cycles after dispatch. If a resource is unbuffered, then
+ // the scheduler will avoid scheduling instructions with conflicting resources
+ // in the same cycle. This is for in-order cpus, or the in-order portion of
+ // an out-of-order cpus.
+ int BufferSize;
+
bool operator==(const MCProcResourceDesc &Other) const {
- return Count == Other.Count && SuperIdx == Other.SuperIdx;
+ return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
+ && BufferSize == Other.BufferSize;
}
};
};
/// Specify the latency in cpu cycles for a particular scheduling class and def
-/// index. Also identify the WriteResources of this def. When the operand
-/// expands to a sequence of writes, this ID is the last write in the sequence.
+/// index. -1 indicates an invalid latency. Heuristics would typically consider
+/// an instruction with invalid latency to have infinite latency. Also identify
+/// the WriteResources of this def. When the operand expands to a sequence of
+/// writes, this ID is the last write in the sequence.
struct MCWriteLatencyEntry {
- unsigned Cycles;
+ int Cycles;
unsigned WriteResourceID;
bool operator==(const MCWriteLatencyEntry &Other) const {
/// microarchitecture to the scheduler in the form of properties. It also
/// optionally refers to scheduler resource tables and itinerary
/// tables. Scheduler resource tables model the latency and cost for each
-/// instruction type. Itinerary tables are an independant mechanism that
+/// instruction type. Itinerary tables are an independent mechanism that
/// provides a detailed reservation table describing each cycle of instruction
/// execution. Subtargets may define any or all of the above categories of data
/// depending on the type of CPU and selected scheduler.
-class MCSchedModel {
-public:
- static MCSchedModel DefaultSchedModel; // For unknown processors.
-
+struct MCSchedModel {
// IssueWidth is the maximum number of instructions that may be scheduled in
// the same per-cycle group.
unsigned IssueWidth;
static const unsigned DefaultIssueWidth = 1;
- // MinLatency is the minimum latency between a register write
- // followed by a data dependent read. This determines which
- // instructions may be scheduled in the same per-cycle group. This
- // is distinct from *expected* latency, which determines the likely
- // critical path but does not guarantee a pipeline
- // hazard. MinLatency can always be overridden by the number of
- // InstrStage cycles.
+ // MicroOpBufferSize is the number of micro-ops that the processor may buffer
+ // for out-of-order execution.
//
- // (-1) Standard in-order processor.
- // Use InstrItinerary OperandCycles as MinLatency.
- // If no OperandCycles exist, then use the cycle of the last InstrStage.
+ // "0" means operations that are not ready in this cycle are not considered
+ // for scheduling (they go in the pending queue). Latency is paramount. This
+ // may be more efficient if many instructions are pending in a schedule.
//
- // (0) Out-of-order processor, or in-order with bundled dependencies.
- // RAW dependencies may be dispatched in the same cycle.
- // Optional InstrItinerary OperandCycles provides expected latency.
+ // "1" means all instructions are considered for scheduling regardless of
+ // whether they are ready in this cycle. Latency still causes issue stalls,
+ // but we balance those stalls against other heuristics.
//
- // (>0) In-order processor with variable latencies.
- // Use the greater of this value or the cycle of the last InstrStage.
- // Optional InstrItinerary OperandCycles provides expected latency.
- // TODO: can't yet specify both min and expected latency per operand.
- int MinLatency;
- static const unsigned DefaultMinLatency = -1;
+ // "> 1" means the processor is out-of-order. This is a machine independent
+ // estimate of highly machine specific characteristics such as the register
+ // renaming pool and reorder buffer.
+ unsigned MicroOpBufferSize;
+ static const unsigned DefaultMicroOpBufferSize = 0;
+
+ // LoopMicroOpBufferSize is the number of micro-ops that the processor may
+ // buffer for optimized loop execution. More generally, this represents the
+ // optimal number of micro-ops in a loop body. A loop may be partially
+ // unrolled to bring the count of micro-ops in the loop body closer to this
+ // number.
+ unsigned LoopMicroOpBufferSize;
+ static const unsigned DefaultLoopMicroOpBufferSize = 0;
// LoadLatency is the expected latency of load instructions.
//
unsigned MispredictPenalty;
static const unsigned DefaultMispredictPenalty = 10;
-private:
+ bool PostRAScheduler; // default value is false
+
+ bool CompleteModel;
+
unsigned ProcID;
const MCProcResourceDesc *ProcResourceTable;
const MCSchedClassDesc *SchedClassTable;
-
unsigned NumProcResourceKinds;
unsigned NumSchedClasses;
-
// Instruction itinerary tables used by InstrItineraryData.
friend class InstrItineraryData;
const InstrItinerary *InstrItineraries;
-public:
- // Default's must be specified as static const literals so that tablegenerated
- // target code can use it in static initializers. The defaults need to be
- // initialized in this default ctor because some clients directly instantiate
- // MCSchedModel instead of using a generated itinerary.
- MCSchedModel(): IssueWidth(DefaultIssueWidth),
- MinLatency(DefaultMinLatency),
- LoadLatency(DefaultLoadLatency),
- HighLatency(DefaultHighLatency),
- MispredictPenalty(DefaultMispredictPenalty),
- ProcID(0), InstrItineraries(0) {}
-
- // Table-gen driven ctor.
- MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
- const InstrItinerary *ii):
- IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
- MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
- SchedClassTable(0), InstrItineraries(ii) {}
+ unsigned getProcessorID() const { return ProcID; }
/// Does this machine model include instruction-level scheduling.
- bool hasInstrSchedModel() const {
- return SchedClassTable;
- }
+ bool hasInstrSchedModel() const { return SchedClassTable; }
- /// Does this machine model include cycle-to-cycle itineraries.
- bool hasInstrItineraries() const {
- return InstrItineraries;
+ /// Return true if this machine model data for all instructions with a
+ /// scheduling class (itinerary class or SchedRW list).
+ bool isComplete() const { return CompleteModel; }
+
+ /// Return true if machine supports out of order execution.
+ bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
+
+ unsigned getNumProcResourceKinds() const {
+ return NumProcResourceKinds;
}
const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
return &SchedClassTable[SchedClassIdx];
}
+
+ /// Returns the default initialized model.
+ static const MCSchedModel &GetDefaultSchedModel() { return Default; }
+ static const MCSchedModel Default;
};
} // End llvm namespace
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