// Number of resources that may be buffered.
//
- // Buffered resources (BufferSize > 0 || BufferSize == -1) may be consumed at
- // some indeterminate cycle after dispatch (e.g. for instructions that may
- // issue out-of-order). Unbuffered resources (BufferSize == 0) always consume
- // their resource some fixed number of cycles after dispatch (e.g. for
- // instruction interlocking that may stall the pipeline).
+ // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
+ // cycle after dispatch. This should be used for out-of-order cpus when
+ // instructions that use this resource can be buffered in a reservaton
+ // station.
+ //
+ // Unbuffered resources (BufferSize == 0) always consume their resource some
+ // fixed number of cycles after dispatch. If a resource is unbuffered, then
+ // the scheduler will avoid scheduling instructions with conflicting resources
+ // in the same cycle. This is for in-order cpus, or the in-order portion of
+ // an out-of-order cpus.
int BufferSize;
bool operator==(const MCProcResourceDesc &Other) const {
/// provides a detailed reservation table describing each cycle of instruction
/// execution. Subtargets may define any or all of the above categories of data
/// depending on the type of CPU and selected scheduler.
-class MCSchedModel {
-public:
- static MCSchedModel DefaultSchedModel; // For unknown processors.
-
+struct MCSchedModel {
// IssueWidth is the maximum number of instructions that may be scheduled in
// the same per-cycle group.
unsigned IssueWidth;
// but we balance those stalls against other heuristics.
//
// "> 1" means the processor is out-of-order. This is a machine independent
- // estimate of highly machine specific characteristics such are the register
+ // estimate of highly machine specific characteristics such as the register
// renaming pool and reorder buffer.
unsigned MicroOpBufferSize;
static const unsigned DefaultMicroOpBufferSize = 0;
+ // LoopMicroOpBufferSize is the number of micro-ops that the processor may
+ // buffer for optimized loop execution. More generally, this represents the
+ // optimal number of micro-ops in a loop body. A loop may be partially
+ // unrolled to bring the count of micro-ops in the loop body closer to this
+ // number.
+ unsigned LoopMicroOpBufferSize;
+ static const unsigned DefaultLoopMicroOpBufferSize = 0;
+
// LoadLatency is the expected latency of load instructions.
//
// If MinLatency >= 0, this may be overriden for individual load opcodes by
unsigned MispredictPenalty;
static const unsigned DefaultMispredictPenalty = 10;
+ bool PostRAScheduler; // default value is false
+
bool CompleteModel;
-private:
unsigned ProcID;
const MCProcResourceDesc *ProcResourceTable;
const MCSchedClassDesc *SchedClassTable;
friend class InstrItineraryData;
const InstrItinerary *InstrItineraries;
-public:
- // Default's must be specified as static const literals so that tablegenerated
- // target code can use it in static initializers. The defaults need to be
- // initialized in this default ctor because some clients directly instantiate
- // MCSchedModel instead of using a generated itinerary.
- MCSchedModel(): IssueWidth(DefaultIssueWidth),
- MicroOpBufferSize(DefaultMicroOpBufferSize),
- LoadLatency(DefaultLoadLatency),
- HighLatency(DefaultHighLatency),
- MispredictPenalty(DefaultMispredictPenalty),
- CompleteModel(true),
- ProcID(0), ProcResourceTable(0), SchedClassTable(0),
- NumProcResourceKinds(0), NumSchedClasses(0),
- InstrItineraries(0) {
- (void)NumProcResourceKinds;
- (void)NumSchedClasses;
- }
-
- // Table-gen driven ctor.
- MCSchedModel(unsigned iw, int mbs, unsigned ll, unsigned hl,
- unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc *pr,
- const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
- const InstrItinerary *ii):
- IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl),
- MispredictPenalty(mp), CompleteModel(cm), ProcID(pi),
- ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr),
- NumSchedClasses(nsc), InstrItineraries(ii) {}
-
unsigned getProcessorID() const { return ProcID; }
/// Does this machine model include instruction-level scheduling.
/// scheduling class (itinerary class or SchedRW list).
bool isComplete() const { return CompleteModel; }
+ /// Return true if machine supports out of order execution.
+ bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
+
unsigned getNumProcResourceKinds() const {
return NumProcResourceKinds;
}
assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
return &SchedClassTable[SchedClassIdx];
}
+
+ /// Returns the default initialized model.
+ static const MCSchedModel &GetDefaultSchedModel() { return Default; }
+ static const MCSchedModel Default;
};
} // End llvm namespace