// takes to recover from a branch misprediction.
unsigned MispredictPenalty;
static const unsigned DefaultMispredictPenalty = 10;
-
+
bool PostRAScheduler; // default value is false
bool CompleteModel;
/// scheduling class (itinerary class or SchedRW list).
bool isComplete() const { return CompleteModel; }
+ /// Return true if machine supports out of order execution.
+ bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
+
unsigned getNumProcResourceKinds() const {
return NumProcResourceKinds;
}
return &SchedClassTable[SchedClassIdx];
}
- // /\brief Returns a default initialiszed mdoel. Used for unknown processors.
- static MCSchedModel GetDefaultSchedModel() {
- return { DefaultIssueWidth,
- DefaultMicroOpBufferSize,
- DefaultLoopMicroOpBufferSize,
- DefaultLoadLatency,
- DefaultHighLatency,
- DefaultMispredictPenalty,
- false,
- true,
- 0,
- nullptr,
- nullptr,
- 0,
- 0,
- nullptr
- };
- }
+ /// Returns the default initialized model.
+ static const MCSchedModel &GetDefaultSchedModel() { return Default; }
+ static const MCSchedModel Default;
};
} // End llvm namespace