#define LLVM_INLINEASM_H
#include "llvm/Value.h"
+#include "llvm/ADT/StringRef.h"
#include <vector>
namespace llvm {
class PointerType;
class FunctionType;
class Module;
+struct InlineAsmKeyType;
+template<class ValType, class ValRefType, class TypeClass, class ConstantClass,
+ bool HasLargeKey>
+class ConstantUniqueMap;
+template<class ConstantClass, class TypeClass, class ValType>
+struct ConstantCreator;
class InlineAsm : public Value {
+ friend struct ConstantCreator<InlineAsm, PointerType, InlineAsmKeyType>;
+ friend class ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&,
+ PointerType, InlineAsm, false>;
+
InlineAsm(const InlineAsm &); // do not implement
void operator=(const InlineAsm&); // do not implement
std::string AsmString, Constraints;
bool HasSideEffects;
+ bool IsAlignStack;
- InlineAsm(const FunctionType *Ty, const std::string &AsmString,
- const std::string &Constraints, bool hasSideEffects);
+ InlineAsm(PointerType *Ty, const std::string &AsmString,
+ const std::string &Constraints, bool hasSideEffects,
+ bool isAlignStack);
virtual ~InlineAsm();
+
+ /// When the ConstantUniqueMap merges two types and makes two InlineAsms
+ /// identical, it destroys one of them with this method.
+ void destroyConstant();
public:
- /// InlineAsm::get - Return the the specified uniqued inline asm string.
+ /// InlineAsm::get - Return the specified uniqued inline asm string.
///
- static InlineAsm *get(const FunctionType *Ty, const std::string &AsmString,
- const std::string &Constraints, bool hasSideEffects);
+ static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
+ StringRef Constraints, bool hasSideEffects,
+ bool isAlignStack = false);
bool hasSideEffects() const { return HasSideEffects; }
+ bool isAlignStack() const { return IsAlignStack; }
/// getType - InlineAsm's are always pointers.
///
- const PointerType *getType() const {
- return reinterpret_cast<const PointerType*>(Value::getType());
+ PointerType *getType() const {
+ return reinterpret_cast<PointerType*>(Value::getType());
}
/// getFunctionType - InlineAsm's are always pointers to functions.
///
- const FunctionType *getFunctionType() const;
+ FunctionType *getFunctionType() const;
const std::string &getAsmString() const { return AsmString; }
const std::string &getConstraintString() const { return Constraints; }
/// the specified constraint string is legal for the type. This returns true
/// if legal, false if not.
///
- static bool Verify(const FunctionType *Ty, const std::string &Constraints);
+ static bool Verify(FunctionType *Ty, StringRef Constraints);
// Constraint String Parsing
enum ConstraintPrefix {
isClobber // '~x'
};
+ typedef std::vector<std::string> ConstraintCodeVector;
+
+ struct SubConstraintInfo {
+ /// MatchingInput - If this is not -1, this is an output constraint where an
+ /// input constraint is required to match it (e.g. "0"). The value is the
+ /// constraint number that matches this one (for example, if this is
+ /// constraint #0 and constraint #4 has the value "0", this will be 4).
+ signed char MatchingInput;
+ /// Code - The constraint code, either the register name (in braces) or the
+ /// constraint letter/number.
+ ConstraintCodeVector Codes;
+ /// Default constructor.
+ SubConstraintInfo() : MatchingInput(-1) {}
+ };
+
+ typedef std::vector<SubConstraintInfo> SubConstraintInfoVector;
+ struct ConstraintInfo;
+ typedef std::vector<ConstraintInfo> ConstraintInfoVector;
+
struct ConstraintInfo {
/// Type - The basic type of the constraint: input/output/clobber
///
/// Code - The constraint code, either the register name (in braces) or the
/// constraint letter/number.
- std::vector<std::string> Codes;
+ ConstraintCodeVector Codes;
+
+ /// isMultipleAlternative - '|': has multiple-alternative constraints.
+ bool isMultipleAlternative;
+
+ /// multipleAlternatives - If there are multiple alternative constraints,
+ /// this array will contain them. Otherwise it will be empty.
+ SubConstraintInfoVector multipleAlternatives;
+
+ /// The currently selected alternative constraint index.
+ unsigned currentAlternativeIndex;
+
+ ///Default constructor.
+ ConstraintInfo();
+
+ /// Copy constructor.
+ ConstraintInfo(const ConstraintInfo &other);
/// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
/// fields in this structure. If the constraint string is not understood,
/// return true, otherwise return false.
- bool Parse(const std::string &Str,
- std::vector<InlineAsm::ConstraintInfo> &ConstraintsSoFar);
+ bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
+
+ /// selectAlternative - Point this constraint to the alternative constraint
+ /// indicated by the index.
+ void selectAlternative(unsigned index);
};
/// ParseConstraints - Split up the constraint string into the specific
/// constraints and their prefixes. If this returns an empty vector, and if
/// the constraint string itself isn't empty, there was an error parsing.
- static std::vector<ConstraintInfo>
- ParseConstraints(const std::string &ConstraintString);
+ static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
/// ParseConstraints - Parse the constraints of this inlineasm object,
/// returning them the same way that ParseConstraints(str) does.
- std::vector<ConstraintInfo>
- ParseConstraints() const {
+ ConstraintInfoVector ParseConstraints() const {
return ParseConstraints(Constraints);
}
return V->getValueID() == Value::InlineAsmVal;
}
+
+ // These are helper methods for dealing with flags in the INLINEASM SDNode
+ // in the backend.
+
+ enum {
+ // Fixed operands on an INLINEASM SDNode.
+ Op_InputChain = 0,
+ Op_AsmString = 1,
+ Op_MDNode = 2,
+ Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack
+ Op_FirstOperand = 4,
+
+ // Fixed operands on an INLINEASM MachineInstr.
+ MIOp_AsmString = 0,
+ MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack
+ MIOp_FirstOperand = 2,
+
+ // Interpretation of the MIOp_ExtraInfo bit field.
+ Extra_HasSideEffects = 1,
+ Extra_IsAlignStack = 2,
+
+ // Inline asm operands map to multiple SDNode / MachineInstr operands.
+ // The first operand is an immediate describing the asm operand, the low
+ // bits is the kind:
+ Kind_RegUse = 1, // Input register, "r".
+ Kind_RegDef = 2, // Output register, "=r".
+ Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
+ Kind_Clobber = 4, // Clobbered register, "~r".
+ Kind_Imm = 5, // Immediate.
+ Kind_Mem = 6, // Memory operand, "m".
+
+ Flag_MatchingOperand = 0x80000000
+ };
+
+ static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
+ assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
+ assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
+ return Kind | (NumOps << 3);
+ }
+
+ /// getFlagWordForMatchingOp - Augment an existing flag word returned by
+ /// getFlagWord with information indicating that this input operand is tied
+ /// to a previous output operand.
+ static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
+ unsigned MatchedOperandNo) {
+ assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
+ assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
+ return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
+ }
+
+ /// getFlagWordForRegClass - Augment an existing flag word returned by
+ /// getFlagWord with the required register class for the following register
+ /// operands.
+ /// A tied use operand cannot have a register class, use the register class
+ /// from the def operand instead.
+ static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
+ // Store RC + 1, reserve the value 0 to mean 'no register class'.
+ ++RC;
+ assert(RC <= 0x7fff && "Too large register class ID");
+ assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
+ return InputFlag | (RC << 16);
+ }
+
+ static unsigned getKind(unsigned Flags) {
+ return Flags & 7;
+ }
+
+ static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
+ static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
+ static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
+ static bool isRegDefEarlyClobberKind(unsigned Flag) {
+ return getKind(Flag) == Kind_RegDefEarlyClobber;
+ }
+ static bool isClobberKind(unsigned Flag) {
+ return getKind(Flag) == Kind_Clobber;
+ }
+
/// getNumOperandRegisters - Extract the number of registers field from the
/// inline asm operand flag.
static unsigned getNumOperandRegisters(unsigned Flag) {
return (Flag & 0xffff) >> 3;
}
- /// isOutputOperandTiedToUse - Return true if the flag of the inline asm
- /// operand indicates it is an output that's matched to an input operand.
- static bool isOutputOperandTiedToUse(unsigned Flag, unsigned &UseIdx) {
- if (Flag & 0x80000000) {
- UseIdx = Flag >> 16;
- return true;
- }
- return false;
+ /// isUseOperandTiedToDef - Return true if the flag of the inline asm
+ /// operand indicates it is an use operand that's matched to a def operand.
+ static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
+ if ((Flag & Flag_MatchingOperand) == 0)
+ return false;
+ Idx = (Flag & ~Flag_MatchingOperand) >> 16;
+ return true;
}
+ /// hasRegClassConstraint - Returns true if the flag contains a register
+ /// class constraint. Sets RC to the register class ID.
+ static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
+ if (Flag & Flag_MatchingOperand)
+ return false;
+ unsigned High = Flag >> 16;
+ // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
+ // stores RC + 1.
+ if (!High)
+ return false;
+ RC = High - 1;
+ return true;
+ }
};
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