Now that the ISel is available, it's possible to create a default instruction

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 01fe6452560108dab3465ddf9c519378918c8fdb..e5d024a892f2a1e3f5bfe9c261ce9bca7d82551f 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -18,7 +18,6 @@
 #include "llvm/Pass.h"
 #include "llvm/Constant.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
-#include <set>
 
 namespace llvm {
   class SelectionDAG;
@@ -42,6 +41,8 @@ public:
   MachineBasicBlock *BB;
 
   SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
+  
+  TargetLowering &getTargetLowering() { return TLI; }
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
@@ -63,6 +64,10 @@ public:
                                             SelectionDAG &DAG) {
     return true;
   }
+
+  /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
+  /// folded during instruction selection?
+  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
   
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
@@ -112,7 +117,7 @@ protected:
   /// by tblgen.  Others should not call it.
   void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
                                      SelectionDAG &DAG);
-  
+
 private:
   SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
                                        Value *V, unsigned Reg);