namespace llvm {
class SelectionDAGLowering;
- class SDOperand;
+ class SDValue;
class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
+ std::vector<SDValue> &OutOps,
SelectionDAG &DAG) {
return true;
}
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
- void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
+ void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
SelectionDAG &DAG);
// Calls to these predicates are generated by tblgen.
- bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+ bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
- bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+ bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const;
private: