#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
+#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
#include "llvm/Constant.h"
#include "llvm/CodeGen/SelectionDAG.h"
namespace llvm {
+ class FastISel;
class SelectionDAGLowering;
class SDValue;
class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
+ class MachineModuleInfo;
+ class DwarfWriter;
class TargetLowering;
+ class TargetInstrInfo;
class FunctionLoweringInfo;
- class HazardRecognizer;
- class CollectorMetadata;
+ class ScheduleHazardRecognizer;
+ class GCFunctionInfo;
class ScheduleDAG;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
+ const TargetMachine &TM;
TargetLowering &TLI;
+ FunctionLoweringInfo *FuncInfo;
+ MachineFunction *MF;
MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
+ SelectionDAGLowering *SDL;
MachineBasicBlock *BB;
AliasAnalysis *AA;
- CollectorMetadata *GCI;
- bool FastISel;
- std::vector<SDNode*> TopOrder;
+ GCFunctionInfo *GFI;
+ bool Fast;
static char ID;
- explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) :
- FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {}
+ explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
+ virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }
unsigned MakeReg(MVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
- virtual void InstructionSelect(SelectionDAG &SD) = 0;
- virtual void InstructionSelectPostProcessing() {}
+ virtual void InstructionSelect() = 0;
- virtual void SelectRootInit() {
- DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
+ void SelectRootInit() {
+ DAGSize = CurDAG->AssignTopologicalOrder();
}
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// OutOps vector.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps,
- SelectionDAG &DAG) {
+ std::vector<SDValue> &OutOps) {
return true;
}
- /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
- /// folded during instruction selection that starts at Root?
- virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
+ /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
+ /// U can be folded during instruction selection that starts at Root and
+ /// folding N is profitable.
+ virtual
+ bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
return true;
}
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG.
- virtual HazardRecognizer *CreateTargetHazardRecognizer();
-
- /// CaseBlock - This structure is used to communicate between SDLowering and
- /// SDISel for the code generation of additional basic blocks needed by multi-
- /// case switch statements.
- struct CaseBlock {
- CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
- MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
- MachineBasicBlock *me)
- : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
- TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
- // CC - the condition code to use for the case block's setcc node
- ISD::CondCode CC;
- // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
- // Emit by default LHS op RHS. MHS is used for range comparisons:
- // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
- Value *CmpLHS, *CmpMHS, *CmpRHS;
- // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
- MachineBasicBlock *TrueBB, *FalseBB;
- // ThisBB - the block into which to emit the code for the setcc and branches
- MachineBasicBlock *ThisBB;
- };
- struct JumpTable {
- JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
- MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
-
- /// Reg - the virtual register containing the index of the jump table entry
- //. to jump to.
- unsigned Reg;
- /// JTI - the JumpTableIndex for this jump table in the function.
- unsigned JTI;
- /// MBB - the MBB into which to emit the code for the indirect jump.
- MachineBasicBlock *MBB;
- /// Default - the MBB of the default bb, which is a successor of the range
- /// check MBB. This is when updating PHI nodes in successors.
- MachineBasicBlock *Default;
- };
- struct JumpTableHeader {
- JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
- bool E = false):
- First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
- uint64_t First;
- uint64_t Last;
- Value *SValue;
- MachineBasicBlock *HeaderBB;
- bool Emitted;
- };
- typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
-
- struct BitTestCase {
- BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
- Mask(M), ThisBB(T), TargetBB(Tr) { }
- uint64_t Mask;
- MachineBasicBlock* ThisBB;
- MachineBasicBlock* TargetBB;
- };
-
- typedef SmallVector<BitTestCase, 3> BitTestInfo;
-
- struct BitTestBlock {
- BitTestBlock(uint64_t F, uint64_t R, Value* SV,
- unsigned Rg, bool E,
- MachineBasicBlock* P, MachineBasicBlock* D,
- const BitTestInfo& C):
- First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
- Parent(P), Default(D), Cases(C) { }
- uint64_t First;
- uint64_t Range;
- Value *SValue;
- unsigned Reg;
- bool Emitted;
- MachineBasicBlock *Parent;
- MachineBasicBlock *Default;
- BitTestInfo Cases;
- };
+ virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
protected:
/// DAGSize - Size of DAG being instruction selected.
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
- void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
- SelectionDAG &DAG);
+ void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
// Calls to these predicates are generated by tblgen.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
private:
void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
- FunctionLoweringInfo &FuncInfo);
- void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
- FunctionLoweringInfo &FuncInfo,
- NodeAllocatorType &NodeAllocator);
-
- void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
- std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
- FunctionLoweringInfo &FuncInfo);
- void CodeGenAndEmitDAG(SelectionDAG &DAG);
- void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
+ MachineModuleInfo *MMI,
+ DwarfWriter *DW,
+ const TargetInstrInfo &TII);
+ void FinishBasicBlock();
+
+ void SelectBasicBlock(BasicBlock *LLVMBB,
+ BasicBlock::iterator Begin,
+ BasicBlock::iterator End);
+ void CodeGenAndEmitDAG();
+ void LowerArguments(BasicBlock *BB);
- void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
+ void ComputeLiveOutVRegInfo();
- /// Pick a safe ordering for instructions for each target node in the
- /// graph.
- ScheduleDAG *Schedule(SelectionDAG &DAG);
+ void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
- /// SwitchCases - Vector of CaseBlock structures used to communicate
- /// SwitchInst code generation information.
- std::vector<CaseBlock> SwitchCases;
+ bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
- /// JTCases - Vector of JumpTable structures which holds necessary information
- /// for emitting a jump tables during SwitchInst code generation.
- std::vector<JumpTableBlock> JTCases;
-
- std::vector<BitTestBlock> BitTestCases;
+ /// Pick a safe ordering for instructions for each target node in the
+ /// graph.
+ ScheduleDAG *Schedule();
};
}
projects / oota-llvm.git / blobdiff