//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
+#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
#include "llvm/Constant.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/SelectionDAG.h"
namespace llvm {
- class SelectionDAG;
+ class FastISel;
class SelectionDAGLowering;
- class SDOperand;
- class SSARegMap;
+ class SDValue;
+ class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
+ class MachineModuleInfo;
+ class DwarfWriter;
class TargetLowering;
+ class TargetInstrInfo;
class FunctionLoweringInfo;
- class HazardRecognizer;
-
+ class ScheduleHazardRecognizer;
+ class GCFunctionInfo;
+ class ScheduleDAG;
+
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
class SelectionDAGISel : public FunctionPass {
public:
+ const TargetMachine &TM;
TargetLowering &TLI;
- SSARegMap *RegMap;
+ FunctionLoweringInfo *FuncInfo;
+ MachineFunction *MF;
+ MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
+ SelectionDAGLowering *SDL;
MachineBasicBlock *BB;
+ AliasAnalysis *AA;
+ GCFunctionInfo *GFI;
+ bool Fast;
+ static char ID;
- SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
+ explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
+ virtual ~SelectionDAGISel();
+
+ TargetLowering &getTargetLowering() { return TLI; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual bool runOnFunction(Function &Fn);
- unsigned MakeReg(MVT::ValueType VT);
+ unsigned MakeReg(MVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
- virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
+ virtual void InstructionSelect() = 0;
+
+ void SelectRootInit() {
+ DAGSize = CurDAG->AssignTopologicalOrder();
+ }
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint code. If this does
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
- SelectionDAG &DAG) {
+ std::vector<SDValue> &OutOps) {
+ return true;
+ }
+
+ /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
+ /// U can be folded during instruction selection that starts at Root and
+ /// folding N is profitable.
+ virtual
+ bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
return true;
}
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG.
- virtual HazardRecognizer *CreateTargetHazardRecognizer();
-
- /// CaseBlock - This structure is used to communicate between SDLowering and
- /// SDISel for the code generation of additional basic blocks needed by multi-
- /// case switch statements.
- struct CaseBlock {
- CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
- MachineBasicBlock *rhs, MachineBasicBlock *me) :
- CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
- // CC - the condition code to use for the case block's setcc node
- ISD::CondCode CC;
- // SwitchV - the value to be switched on, 'foo' in switch(foo)
- Value *SwitchV;
- // CaseC - the constant the setcc node will compare against SwitchV
- Constant *CaseC;
- // LHSBB - the block to branch to if the setcc is true
- MachineBasicBlock *LHSBB;
- // RHSBB - the block to branch to if the setcc is false
- MachineBasicBlock *RHSBB;
- // ThisBB - the blcok into which to emit the code for the setcc and branches
- MachineBasicBlock *ThisBB;
- };
+ virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
protected:
- /// Pick a safe ordering and emit instructions for each target node in the
- /// graph.
- void ScheduleAndEmitDAG(SelectionDAG &DAG);
-
+ /// DAGSize - Size of DAG being instruction selected.
+ ///
+ unsigned DAGSize;
+
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
- void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
- SelectionDAG &DAG);
+ void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
+
+ // Calls to these predicates are generated by tblgen.
+ bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
+ bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) const;
private:
- SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
- Value *V, unsigned Reg);
- void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
- FunctionLoweringInfo &FuncInfo);
-
- void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
- std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
- FunctionLoweringInfo &FuncInfo);
- void CodeGenAndEmitDAG(SelectionDAG &DAG);
- void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
- std::vector<SDOperand> &UnorderedChains);
-
- /// SwitchCases - Vector of CaseBlock structures used to communicate
- /// SwitchInst code generation information.
- std::vector<CaseBlock> SwitchCases;
+ void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
+ MachineModuleInfo *MMI,
+ DwarfWriter *DW,
+ const TargetInstrInfo &TII);
+ void FinishBasicBlock();
+
+ void SelectBasicBlock(BasicBlock *LLVMBB,
+ BasicBlock::iterator Begin,
+ BasicBlock::iterator End);
+ void CodeGenAndEmitDAG();
+ void LowerArguments(BasicBlock *BB);
+
+ void ComputeLiveOutVRegInfo();
+
+ void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
+
+ bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
+
+ /// Pick a safe ordering for instructions for each target node in the
+ /// graph.
+ ScheduleDAG *Schedule();
};
}
projects / oota-llvm.git / blobdiff