/// TargetSchedModel provides an interface to the machine model.
TargetSchedModel SchedModel;
+ /// isPostRA flag indicates vregs cannot be present.
+ bool IsPostRA;
+
/// True if the DAG builder should remove kill flags (in preparation for
/// rescheduling).
bool RemoveKillFlags;
public:
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo *mli,
+ bool IsPostRAFlag,
bool RemoveKillFlags = false,
LiveIntervals *LIS = nullptr);
~ScheduleDAGInstrs() override {}
+ bool isPostRA() const { return IsPostRA; }
+
/// \brief Expose LiveIntervals for use in DAG mutators and such.
LiveIntervals *getLIS() const { return LIS; }