#include "llvm/ADT/PointerIntPair.h"
namespace llvm {
- struct SUnit;
+ class SUnit;
class MachineConstantPool;
class MachineFunction;
class MachineModuleInfo;
class MachineInstr;
class TargetRegisterInfo;
class ScheduleDAG;
- class SelectionDAG;
class SDNode;
class TargetInstrInfo;
class TargetInstrDesc;
};
/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
- struct SUnit {
+ class SUnit {
private:
SDNode *Node; // Representative node.
MachineInstr *Instr; // Alternatively, a MachineInstr.
bool isTwoAddress : 1; // Is a two-address instruction.
bool isCommutable : 1; // Is a commutable instruction.
bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
+ bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
bool isPending : 1; // True once pending.
bool isAvailable : 1; // True once available.
bool isScheduled : 1; // True once scheduled.
bool isScheduleHigh : 1; // True if preferable to schedule high.
+ bool isCloned : 1; // True if this node has been cloned.
private:
bool isDepthCurrent : 1; // True if Depth is current.
bool isHeightCurrent : 1; // True if Height is current.
: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
- isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
- Depth(0), Height(0),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {}
/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
- isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
- Depth(0), Height(0),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
+ CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+ /// SUnit - Construct a placeholder SUnit.
+ SUnit()
+ : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
+ Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+ isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
+ isPending(false), isAvailable(false), isScheduled(false),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {}
/// setNode - Assign the representative SDNode for this SUnit.
class ScheduleDAG {
public:
- SelectionDAG *DAG; // DAG of the current basic block
- MachineBasicBlock *BB; // Current basic block
+ MachineBasicBlock *BB; // The block in which to insert instructions.
+ MachineBasicBlock::iterator InsertPos;// The position to insert instructions.
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info
- TargetLowering *TLI; // Target lowering info
+ const TargetLowering *TLI; // Target lowering info
MachineFunction &MF; // Machine function
MachineRegisterInfo &MRI; // Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool
std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
// represent noop instructions.
std::vector<SUnit> SUnits; // The scheduling units.
+ SUnit EntrySU; // Special node for the region entry.
+ SUnit ExitSU; // Special node for the region exit.
explicit ScheduleDAG(MachineFunction &mf);
///
void viewGraph();
- /// Run - perform scheduling.
- ///
- void Run(SelectionDAG *DAG, MachineBasicBlock *MBB);
-
- /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
- /// to form the scheduling dependency graph.
- ///
- virtual void BuildSchedGraph() = 0;
-
- /// ComputeLatency - Compute node latency.
+ /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
+ /// according to the order specified in Sequence.
///
- virtual void ComputeLatency(SUnit *SU) = 0;
-
- protected:
- /// EmitNoop - Emit a noop instruction.
- ///
- void EmitNoop();
-
- public:
virtual MachineBasicBlock *EmitSchedule() = 0;
void dumpSchedule() const;
- /// Schedule - Order nodes according to selected style, filling
- /// in the Sequence member.
- ///
- virtual void Schedule() = 0;
-
virtual void dumpNode(const SUnit *SU) const = 0;
/// getGraphNodeLabel - Return a label for an SUnit node in a visualization
#endif
protected:
- void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
+ /// Run - perform scheduling.
+ ///
+ void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
- void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
+ /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
+ /// to form the scheduling dependency graph.
+ ///
+ virtual void BuildSchedGraph() = 0;
+
+ /// ComputeLatency - Compute node latency.
+ ///
+ virtual void ComputeLatency(SUnit *SU) = 0;
+
+ /// Schedule - Order nodes according to selected style, filling
+ /// in the Sequence member.
+ ///
+ virtual void Schedule() = 0;
/// ForceUnitLatencies - Return true if all scheduling edges should be given a
/// latency value of one. The default is to return false; schedulers may
/// override this as needed.
virtual bool ForceUnitLatencies() const { return false; }
+ /// EmitNoop - Emit a noop instruction.
+ ///
+ void EmitNoop();
+
+ void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
+
+ void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
+
private:
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
/// physical register has only a single copy use, then coalesced the copy
projects / oota-llvm.git / blobdiff