/// PhysRegUseDefLists - This is an array of the head of the use/def list for
/// physical registers.
- std::vector<MachineOperand *> PhysRegUseDefLists;
+ std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
/// getRegUseDefListHead - Return the head pointer for the register use/def
/// list for the specified virtual or physical register.
return MO->Contents.Reg.Next;
}
- /// UsedRegUnits - This is a bit vector that is computed and set by the
- /// register allocator, and must be kept up to date by passes that run after
- /// register allocation (though most don't modify this). This is used
- /// so that the code generator knows which callee save registers to save and
- /// for other target specific uses.
- /// This vector has bits set for register units that are modified in the
- /// current function. It doesn't include registers clobbered by function
- /// calls with register mask operands.
- BitVector UsedRegUnits;
-
/// UsedPhysRegMask - Additional used physregs including aliases.
/// This bit vector represents all the registers clobbered by function calls.
- /// It can model things that UsedRegUnits can't, such as function calls that
- /// clobber ymm7 but preserve the low half in xmm7.
BitVector UsedPhysRegMask;
/// ReservedRegs - This is a bit vector of reserved registers. The target
/// second element.
std::vector<std::pair<unsigned, unsigned> > LiveIns;
- MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
- void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
+ MachineRegisterInfo(const MachineRegisterInfo&) = delete;
+ void operator=(const MachineRegisterInfo&) = delete;
public:
explicit MachineRegisterInfo(const MachineFunction *MF);
/// information.
void invalidateLiveness() { TracksLiveness = false; }
- bool tracksSubRegLiveness() const { return TracksSubRegLiveness; }
+ /// Returns true if liveness for register class @p RC should be tracked at
+ /// the subregister level.
+ bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
+ return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
+ }
+ bool shouldTrackSubRegLiveness(unsigned VReg) const {
+ assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
+ return shouldTrackSubRegLiveness(*getRegClass(VReg));
+ }
+ bool subRegLivenessEnabled() const {
+ return TracksSubRegLiveness;
+ }
void enableSubRegLiveness(bool Enable = true) {
TracksSubRegLiveness = Enable;
static reg_iterator reg_end() { return reg_iterator(nullptr); }
inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
- return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
+ return make_range(reg_begin(Reg), reg_end());
}
/// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
inline iterator_range<reg_instr_iterator>
reg_instructions(unsigned Reg) const {
- return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
- reg_instr_end());
+ return make_range(reg_instr_begin(Reg), reg_instr_end());
}
/// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
}
inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
- return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
- reg_bundle_end());
+ return make_range(reg_bundle_begin(Reg), reg_bundle_end());
}
/// reg_empty - Return true if there are no instructions using or defining the
inline iterator_range<reg_nodbg_iterator>
reg_nodbg_operands(unsigned Reg) const {
- return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
- reg_nodbg_end());
+ return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
}
/// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
inline iterator_range<reg_instr_nodbg_iterator>
reg_nodbg_instructions(unsigned Reg) const {
- return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
- reg_instr_nodbg_end());
+ return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
}
/// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
return reg_bundle_nodbg_iterator(nullptr);
}
- inline iterator_range<reg_bundle_nodbg_iterator>
+ inline iterator_range<reg_bundle_nodbg_iterator>
reg_nodbg_bundles(unsigned Reg) const {
- return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
- reg_bundle_nodbg_end());
+ return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
}
/// reg_nodbg_empty - Return true if the only instructions using or defining
static def_iterator def_end() { return def_iterator(nullptr); }
inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
- return iterator_range<def_iterator>(def_begin(Reg), def_end());
+ return make_range(def_begin(Reg), def_end());
}
/// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
inline iterator_range<def_instr_iterator>
def_instructions(unsigned Reg) const {
- return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
- def_instr_end());
+ return make_range(def_instr_begin(Reg), def_instr_end());
}
/// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
}
inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
- return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
- def_bundle_end());
+ return make_range(def_bundle_begin(Reg), def_bundle_end());
}
/// def_empty - Return true if there are no instructions defining the
static use_iterator use_end() { return use_iterator(nullptr); }
inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
- return iterator_range<use_iterator>(use_begin(Reg), use_end());
+ return make_range(use_begin(Reg), use_end());
}
/// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
inline iterator_range<use_instr_iterator>
use_instructions(unsigned Reg) const {
- return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
- use_instr_end());
+ return make_range(use_instr_begin(Reg), use_instr_end());
}
/// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
}
inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
- return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
- use_bundle_end());
+ return make_range(use_bundle_begin(Reg), use_bundle_end());
}
/// use_empty - Return true if there are no instructions using the specified
inline iterator_range<use_nodbg_iterator>
use_nodbg_operands(unsigned Reg) const {
- return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
- use_nodbg_end());
+ return make_range(use_nodbg_begin(Reg), use_nodbg_end());
}
/// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
inline iterator_range<use_instr_nodbg_iterator>
use_nodbg_instructions(unsigned Reg) const {
- return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
- use_instr_nodbg_end());
+ return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
}
/// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
inline iterator_range<use_bundle_nodbg_iterator>
use_nodbg_bundles(unsigned Reg) const {
- return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
- use_bundle_nodbg_end());
+ return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
}
/// use_nodbg_empty - Return true if there are no non-Debug instructions
/// apply sub registers to ToReg in order to obtain a final/proper physical
/// register.
void replaceRegWith(unsigned FromReg, unsigned ToReg);
-
+
/// getVRegDef - Return the machine instr that defines the specified virtual
/// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition.
/// virtual register, for example after removing instructions or splitting
/// the live range.
///
- bool recomputeRegClass(unsigned Reg, const TargetMachine&);
+ bool recomputeRegClass(unsigned Reg);
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
/// setRegAllocationHint - Specify a register allocation hint for the
/// specified virtual register.
- void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
- RegAllocHints[Reg].first = Type;
- RegAllocHints[Reg].second = PrefReg;
+ void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
+ assert(TargetRegisterInfo::isVirtualRegister(VReg));
+ RegAllocHints[VReg].first = Type;
+ RegAllocHints[VReg].second = PrefReg;
+ }
+
+ /// Specify the preferred register allocation hint for the specified virtual
+ /// register.
+ void setSimpleHint(unsigned VReg, unsigned PrefReg) {
+ setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
}
/// getRegAllocationHint - Return the register allocation hint for the
/// specified virtual register.
std::pair<unsigned, unsigned>
- getRegAllocationHint(unsigned Reg) const {
- return RegAllocHints[Reg];
+ getRegAllocationHint(unsigned VReg) const {
+ assert(TargetRegisterInfo::isVirtualRegister(VReg));
+ return RegAllocHints[VReg];
}
/// getSimpleHint - Return the preferred register allocation hint, or 0 if a
/// standard simple hint (Type == 0) is not set.
- unsigned getSimpleHint(unsigned Reg) const {
- std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
+ unsigned getSimpleHint(unsigned VReg) const {
+ assert(TargetRegisterInfo::isVirtualRegister(VReg));
+ std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
return Hint.first ? 0 : Hint.second;
}
/// deleted during LiveDebugVariables analysis.
void markUsesInDebugValueAsUndef(unsigned Reg) const;
- //===--------------------------------------------------------------------===//
- // Physical Register Use Info
- //===--------------------------------------------------------------------===//
-
- /// isPhysRegUsed - Return true if the specified register is used in this
- /// function. Also check for clobbered aliases and registers clobbered by
- /// function calls with register mask operands.
- ///
- /// This only works after register allocation. It is primarily used by
- /// PrologEpilogInserter to determine which callee-saved registers need
- /// spilling.
- bool isPhysRegUsed(unsigned Reg) const {
- if (UsedPhysRegMask.test(Reg))
- return true;
- for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
- Units.isValid(); ++Units)
- if (UsedRegUnits.test(*Units))
- return true;
- return false;
- }
+ /// Return true if the specified register is modified in this function.
+ /// This checks that no defining machine operands exist for the register or
+ /// any of its aliases. Definitions found on functions marked noreturn are
+ /// ignored. The register is also considered modified when it is set in the
+ /// UsedPhysRegMask.
+ bool isPhysRegModified(unsigned PhysReg) const;
- /// Mark the specified register unit as used in this function.
- /// This should only be called during and after register allocation.
- void setRegUnitUsed(unsigned RegUnit) {
- UsedRegUnits.set(RegUnit);
- }
-
- /// setPhysRegUsed - Mark the specified register used in this function.
- /// This should only be called during and after register allocation.
- void setPhysRegUsed(unsigned Reg) {
- for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
- Units.isValid(); ++Units)
- UsedRegUnits.set(*Units);
- }
+ /// Return true if the specified register is modified or read in this
+ /// function. This checks that no machine operands exist for the register or
+ /// any of its aliases. The register is also considered used when it is set
+ /// in the UsedPhysRegMask.
+ bool isPhysRegUsed(unsigned PhysReg) const;
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
/// This corresponds to the bit mask attached to register mask operands.
UsedPhysRegMask.setBitsNotInMask(RegMask);
}
- /// setPhysRegUnused - Mark the specified register unused in this function.
- /// This should only be called during and after register allocation.
- void setPhysRegUnused(unsigned Reg) {
- UsedPhysRegMask.reset(Reg);
- for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
- Units.isValid(); ++Units)
- UsedRegUnits.reset(*Units);
- }
+ const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
+ void setUsedPhysRegMask(BitVector &Mask) { UsedPhysRegMask = Mask; }
//===--------------------------------------------------------------------===//
// Reserved Register Info
/// Returns a mask covering all bits that can appear in lane masks of
/// subregisters of the virtual register @p Reg.
- unsigned getMaxLaneMaskForVReg(unsigned Reg) const;
+ LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
/// defusechain_iterator - This class provides iterator support for machine
/// operands in the function that use or define a specific register. If
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::pointer pointer;
- defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
defusechain_iterator() : Op(nullptr) {}
bool operator==(const defusechain_iterator &x) const {
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::pointer pointer;
- defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
defusechain_instr_iterator() : Op(nullptr) {}
bool operator==(const defusechain_instr_iterator &x) const {
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