[SelectionDAG] Force cycle detection in AssignTopologicalOrder before aborting

[oota-llvm.git] / include / llvm / CodeGen / LiveIntervalUnion.h

diff --git a/include/llvm/CodeGen/LiveIntervalUnion.h b/include/llvm/CodeGen/LiveIntervalUnion.h
index 615b339bd79cc096a14a97647cc2c2f975a1173c..2f40509a11115925f29ffaa615b52f269f431ec6 100644 (file)
--- a/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -32,7 +32,7 @@ typedef SparseBitVector<128> LiveVirtRegBitSet;
 
 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
 inline bool
-overlap(const LiveRange &VRSeg,
+overlap(const LiveInterval::Segment &VRSeg,
         const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
   return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
 }
@@ -122,8 +122,8 @@ public:
     {}
 
     void clear() {
-      LiveUnion = NULL;
-      VirtReg = NULL;
+      LiveUnion = nullptr;
+      VirtReg = nullptr;
       InterferingVRegs.clear();
       CheckedFirstInterference = false;
       SeenAllInterferences = false;
@@ -182,7 +182,7 @@ public:
     unsigned Size;
     LiveIntervalUnion *LIUs;
   public:
-    Array() : Size(0), LIUs(0) {}
+    Array() : Size(0), LIUs(nullptr) {}
     ~Array() { clear(); }
 
     // Initialize the array to have Size entries.