Add an "alignment" field to the MachineFunction object. It makes more sense to

[oota-llvm.git] / include / llvm / CodeGen / FastISel.h

diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index 95280c9474a6eebd0af025877188ed9c8e838eac..c7b1a42d06b627d5328bafbc7d419ca90b442d27 100644 (file)
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -14,16 +14,21 @@
 #ifndef LLVM_CODEGEN_FASTISEL_H
 #define LLVM_CODEGEN_FASTISEL_H
 
-#include "llvm/BasicBlock.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 
 namespace llvm {
 
+class AllocaInst;
 class ConstantFP;
+class Instruction;
 class MachineBasicBlock;
 class MachineConstantPool;
 class MachineFunction;
+class MachineFrameInfo;
+class MachineModuleInfo;
+class DwarfWriter;
 class MachineRegisterInfo;
 class TargetData;
 class TargetInstrInfo;
@@ -40,21 +45,46 @@ protected:
   DenseMap<const Value *, unsigned> LocalValueMap;
   DenseMap<const Value *, unsigned> &ValueMap;
   DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
+  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
+#ifndef NDEBUG
+  SmallSet<Instruction*, 8> &CatchInfoLost;
+#endif
   MachineFunction &MF;
+  MachineModuleInfo *MMI;
+  DwarfWriter *DW;
   MachineRegisterInfo &MRI;
+  MachineFrameInfo &MFI;
+  MachineConstantPool &MCP;
+  DebugLoc DL;
   const TargetMachine &TM;
   const TargetData &TD;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
 
 public:
-  /// setCurrentBlock - Set the current block, to which generated
-  /// machine instructions will be appended.
+  /// startNewBlock - Set the current block to which generated machine
+  /// instructions will be appended, and clear the local CSE map.
+  ///
+  void startNewBlock(MachineBasicBlock *mbb) {
+    setCurrentBlock(mbb);
+    LocalValueMap.clear();
+  }
+
+  /// setCurrentBlock - Set the current block to which generated machine
+  /// instructions will be appended.
   ///
   void setCurrentBlock(MachineBasicBlock *mbb) {
     MBB = mbb;
   }
 
+  /// setCurDebugLoc - Set the current debug location information, which is used
+  /// when creating a machine instruction.
+  ///
+  void setCurDebugLoc(DebugLoc dl) { DL = dl; }
+
+  /// getCurDebugLoc() - Return current debug location information.
+  DebugLoc getCurDebugLoc() const { return DL; }
+
   /// SelectInstruction - Do "fast" instruction selection for the given
   /// LLVM IR instruction, and append generated machine instructions to
   /// the current block. Return true if selection was successful.
@@ -80,12 +110,29 @@ public:
   /// be assigned the value for the given LLVM value.
   unsigned getRegForValue(Value *V);
 
+  /// lookUpRegForValue - Look up the value to see if its value is already
+  /// cached in a register. It may be defined by instructions across blocks or
+  /// defined locally.
+  unsigned lookUpRegForValue(Value *V);
+
+  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
+  /// takes care of truncating or sign-extending the given getelementptr
+  /// index value.
+  unsigned getRegForGEPIndex(Value *V);
+
   virtual ~FastISel();
 
 protected:
   FastISel(MachineFunction &mf,
+           MachineModuleInfo *mmi,
+           DwarfWriter *dw,
            DenseMap<const Value *, unsigned> &vm,
-           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm);
+           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
+           DenseMap<const AllocaInst *, int> &am
+#ifndef NDEBUG
+           , SmallSet<Instruction*, 8> &cil
+#endif
+           );
 
   /// FastEmit_r - This method is called by target-independent code
   /// to request that an instruction with the given type and opcode
@@ -220,15 +267,33 @@ protected:
                           uint64_t Imm);
 
   /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
-  /// from a specified index of a superregister.
-  unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
+  /// from a specified index of a superregister to a specified type.
+  unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
+                                      unsigned Op0, uint32_t Idx);
+
+  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
+  /// with all but the least significant bit set to zero.
+  unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
+                              unsigned Op);
+
+  /// FastEmitBranch - Emit an unconditional branch to the given block,
+  /// unless it is the immediate (fall-through) successor, and update
+  /// the CFG.
+  void FastEmitBranch(MachineBasicBlock *MBB);
 
-  void UpdateValueMap(Value* I, unsigned Reg);
+  unsigned UpdateValueMap(Value* I, unsigned Reg);
 
   unsigned createResultReg(const TargetRegisterClass *RC);
   
-  virtual unsigned TargetSelectConstantPoolLoad(Constant* C,
-                                                MachineConstantPool* MCP) {
+  /// TargetMaterializeConstant - Emit a constant in a register using 
+  /// target-specific logic, such as constant pool loads.
+  virtual unsigned TargetMaterializeConstant(Constant* C) {
+    return 0;
+  }
+
+  /// TargetMaterializeAlloca - Emit an alloca address in a register using
+  /// target-specific logic.
+  virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
     return 0;
   }
 
@@ -237,6 +302,8 @@ private:
 
   bool SelectGetElementPtr(User *I);
 
+  bool SelectCall(User *I);
+
   bool SelectBitCast(User *I);
   
   bool SelectCast(User *I, ISD::NodeType Opcode);