#ifndef LLVM_CODEGEN_FASTISEL_H
#define LLVM_CODEGEN_FASTISEL_H
-#include "llvm/BasicBlock.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
namespace llvm {
class AllocaInst;
class ConstantFP;
+class Instruction;
class MachineBasicBlock;
class MachineConstantPool;
class MachineFunction;
class MachineFrameInfo;
class MachineModuleInfo;
+class DwarfWriter;
class MachineRegisterInfo;
class TargetData;
class TargetInstrInfo;
DenseMap<const Value *, unsigned> &ValueMap;
DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
DenseMap<const AllocaInst *, int> &StaticAllocaMap;
+#ifndef NDEBUG
+ SmallSet<Instruction*, 8> &CatchInfoLost;
+#endif
MachineFunction &MF;
MachineModuleInfo *MMI;
+ DwarfWriter *DW;
MachineRegisterInfo &MRI;
MachineFrameInfo &MFI;
MachineConstantPool &MCP;
+ DebugLoc DL;
const TargetMachine &TM;
const TargetData &TD;
const TargetInstrInfo &TII;
const TargetLowering &TLI;
public:
- /// setCurrentBlock - Set the current block, to which generated
- /// machine instructions will be appended.
+ /// startNewBlock - Set the current block to which generated machine
+ /// instructions will be appended, and clear the local CSE map.
+ ///
+ void startNewBlock(MachineBasicBlock *mbb) {
+ setCurrentBlock(mbb);
+ LocalValueMap.clear();
+ }
+
+ /// setCurrentBlock - Set the current block to which generated machine
+ /// instructions will be appended.
///
void setCurrentBlock(MachineBasicBlock *mbb) {
MBB = mbb;
- LocalValueMap.clear();
}
+ /// setCurDebugLoc - Set the current debug location information, which is used
+ /// when creating a machine instruction.
+ ///
+ void setCurDebugLoc(DebugLoc dl) { DL = dl; }
+
+ /// getCurDebugLoc() - Return current debug location information.
+ DebugLoc getCurDebugLoc() const { return DL; }
+
/// SelectInstruction - Do "fast" instruction selection for the given
/// LLVM IR instruction, and append generated machine instructions to
/// the current block. Return true if selection was successful.
/// defined locally.
unsigned lookUpRegForValue(Value *V);
+ /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
+ /// takes care of truncating or sign-extending the given getelementptr
+ /// index value.
+ unsigned getRegForGEPIndex(Value *V);
+
virtual ~FastISel();
protected:
FastISel(MachineFunction &mf,
MachineModuleInfo *mmi,
+ DwarfWriter *dw,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am);
+ DenseMap<const AllocaInst *, int> &am
+#ifndef NDEBUG
+ , SmallSet<Instruction*, 8> &cil
+#endif
+ );
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
- virtual unsigned FastEmit_(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
- virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_r(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
- virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rr(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_ri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm);
/// to request that an instruction with the given type, opcode, and
/// register and floating-point immediate operands be emitted.
///
- virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rf(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm);
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1, uint64_t Imm);
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_ri_(MVT::SimpleValueType VT,
+ unsigned FastEmit_ri_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- MVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
/// to emit an instruction with an immediate operand using FastEmit_rf.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_rf_(MVT::SimpleValueType VT,
+ unsigned FastEmit_rf_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- MVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_i - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// immediate operand be emitted.
- virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_i(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
uint64_t Imm);
/// FastEmit_f - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// floating-point immediate operand be emitted.
- virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_f(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
ConstantFP *FPImm);
uint64_t Imm);
/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
- /// from a specified index of a superregister.
- unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
+ /// from a specified index of a superregister to a specified type.
+ unsigned FastEmitInst_extractsubreg(MVT RetVT,
+ unsigned Op0, uint32_t Idx);
+
+ /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
+ /// with all but the least significant bit set to zero.
+ unsigned FastEmitZExtFromI1(MVT VT,
+ unsigned Op);
/// FastEmitBranch - Emit an unconditional branch to the given block,
/// unless it is the immediate (fall-through) successor, and update
/// the CFG.
void FastEmitBranch(MachineBasicBlock *MBB);
- void UpdateValueMap(Value* I, unsigned Reg);
+ unsigned UpdateValueMap(Value* I, unsigned Reg);
unsigned createResultReg(const TargetRegisterClass *RC);
private:
bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
+ bool SelectFNeg(User *I);
+
bool SelectGetElementPtr(User *I);
bool SelectCall(User *I);
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